Posts for si-list, 07-2001

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  1. » [SI-LIST] Re: Validation of XTK results for clock skews, Suchitha . V
  2. » [SI-LIST] ADDITIONAL PCI CLOCKS, Chandan
  3. » [SI-LIST] High performance materials, Chris Mesibov
  4. » [SI-LIST] Re: ADDITIONAL PCI CLOCKS, Robert_Washburn
  5. » [SI-LIST] Which computing platform for (Ansoft/Pacific Numerix) TPA, grhare
  6. » [SI-LIST] Re: Decoupling, Larry Smith
  7. » [SI-LIST] FR4, Rich Peyton
  8. » [SI-LIST] si-list hardware failure on 7/7 thru 7/9, Ray Anderson
  9. » [SI-LIST] Re: FR4, Greim, Michael
  10. » [SI-LIST] Temperature vs. performance in different type of processes., =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
  11. » [SI-LIST] stats si-list, marko . pulli
  12. » [SI-LIST] Re: Temperature vs. performance in different type of processes., Dagostino, Tom
  13. » [SI-LIST] Re: power plane spacing, S. Weir
  14. » [SI-LIST] post layout SI analysis, Andrew H.Barr
  15. » [SI-LIST] Board to Board connetcions using Coax cables, Sreejith Varma
  16. » [SI-LIST] Re: post layout SI analysis, Beal, Weston
  17. » [SI-LIST] Re: Board to Board connetcions using Coax cables, Sreejith Varma
  18. » [SI-LIST] Primary Signal Integrity Hardware Tools, EADS,RICK (A-ColSprings,ex1)
  19. » [SI-LIST] Re: Primary Signal Integrity Hardware Tools, Zabinski, Patrick J.
  20. » [SI-LIST] extraction of RLGC matrices from Sigexplorer, Peter LaFlamme
  21. » [SI-LIST] Re: extraction of RLGC matrices from Sigexplorer, ruston, matt
  22. » [SI-LIST] On-chip Terminations, Patrick Francq
  23. » [SI-LIST] Re: On-chip Terminations, Michael Nudelman
  24. » [SI-LIST] IC Receiver Design for Low Jitter, Chuck Hill
  25. » [SI-LIST] Re: IC Receiver Design for Low Jitter, ABOULHOUDA,SAMIR (A-England,ex1)
  26. » [SI-LIST] Signal Integrity Position - ASIC : Cisco Systems, Inc. San Jose, CA, Zhiping Yang
  27. » [SI-LIST] Re: Temperature vs. performance in different type of processes., Volk, Andrew M
  28. » [SI-LIST] In EBD model?, Inmyung Song
  29. » [SI-LIST] Production testing of loaded PCB's power supply impedance, Peter Baxter
  30. » [SI-LIST] Re: Production testing of loaded PCB's power supply impedance, Greim, Michael
  31. » [SI-LIST] Re: In EBD model?, Beal, Weston
  32. » [SI-LIST] Injecting noise into a plane, Alokby, Ahmed
  33. » [SI-LIST] Re: Injecting noise into a plane, Dagostino, Tom
  34. » [SI-LIST] Buried resister in High Speed Digital Design?, Inmyung Song
  35. » [SI-LIST] Clock skew measurement using XTK simulation tool, Goutham . S
  36. » [SI-LIST] IBIS model, Goutham . S
  37. » [SI-LIST] Oscilloscope for POST SI Analysis, Adam Klein
  38. » [SI-LIST] High Speed Inter-board connections, Ron Kane
  39. » [SI-LIST] Controlled impedance PCB question, Allan Davidson
  40. » [SI-LIST] Question about package models, Allan Davidson
  41. » [SI-LIST] Re: Controlled impedance PCB question, Zabinski, Patrick J.
  42. » [SI-LIST] Re: Question about package models, Zabinski, Patrick J.
  43. » [SI-LIST] Flash memory, Seol Byongsu
  44. » [SI-LIST] Mictor probes and 'high' speed/sensitive signals, S Tatlow
  45. » [SI-LIST] tools for assembly cost and metrics of printed circuit boards, jan . vercammen . jv1
  46. » [SI-LIST] set si-list vacation, Ilkka Lehikoinen
  47. » [SI-LIST] System Designers w/ SI skills needed in Santa Clara, CA, Mark Apton
  48. » [SI-LIST] Last Day in Force, Senthil . Selvam
  49. » [SI-LIST] PCB material with er=2.5?, David Instone
  50. » [SI-LIST] LICA in flip chip BGAs, Yuan Li
  51. » [SI-LIST] ac drive strength, Peterson, James F (FL51)
  52. » [SI-LIST] need some help, Michael Allen
  53. » [SI-LIST] Re: need some help, Kai Keskinen
  54. » [SI-LIST] AGP model, =?big5?b?Um9nZXIuV3UgKKdkrVqqTCk=?=
  55. » [SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION, Kai, Francis
  56. » [SI-LIST] Re: SpecctraQuest, Todd Westerhoff
  57. » [SI-LIST] test message - Ignore and Delete, Ray Anderson
  58. » [SI-LIST] diff pair questions, signal hoss
  59. » [SI-LIST] si-list administrivia, Ray Anderson
  60. » [SI-LIST] Re: si-list administrivia, Beal, Weston
  61. » [SI-LIST] AMD Forms Hyper-Transport I/O Consortium, Jonathan Dowling
  62. » [SI-LIST] Re: diff pair questions, Daniel, Erik S.
  63. » [SI-LIST] IBIS Model for Multi-Chip Package, Aaron Frank
  64. » [SI-LIST] Re: IBIS Model for Multi-Chip Package, Peters, Stephen
  65. » [SI-LIST] Results of the "Reply To:" survey - Option B wins, Ray Anderson
  66. » [SI-LIST] EMI and Power plane card edge clearance distance, Stacy L Gore
  67. » [SI-LIST] Re: Results of the "Reply To:" survey - Option B wins, EMCCOMPLY
  68. » [SI-LIST] LVDS Glitch Problem, Denomme, Paul S.
  69. » [SI-LIST] Re: Tool Recommendations?, Doug Hopperstad
  70. » [SI-LIST] Re: ac drive strength, Muranyi, Arpad
  71. » [SI-LIST] HSPICE to print HEX question, dan hariton
  72. » [SI-LIST] IBIS and device performance, Todd Westerhoff
  73. » [SI-LIST] Creating IBIS Electrical Board Descriptions, Aaron Frank
  74. » [SI-LIST] Rise time calculation, Jinto N.Jose
  75. » [SI-LIST] Alloy-42 ur and sigma ..., Neeraj Pendse
  76. » [SI-LIST] Re: Alloy-42 ur and sigma ..., Rich Peyton
  77. » [SI-LIST] PCI Bus Ringing, Overshoot, Simba Julian
  78. » [SI-LIST] Fiber Channel simulation, =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
  79. » [SI-LIST] Re: differential trace mismatch, Martin.J Thompson
  80. » [SI-LIST] Design with DDR (SSTL-2) memory, Ravinder Ajmani
  81. » [SI-LIST] Re: Placement of decoupling capacitors, Khalid Ansari