[SI-LIST] Re: decoupling
- From: Larry Smith <ldsmith@xxxxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 11 Jul 2001 15:11:21 -0700 (PDT)
Khalid - Larry Miller has already provided an answer that I pretty much
agree with. Discrete decoupling capacitors are rapidly loosing their
effectiveness between 200 and 400 MHz because of their inductance. We
have been able to obtain a total mounted inductance (ESL) of about
500pH for discrete capacitors. With further improvements, we may be
able to drop that to 350pH. But at 400 MHz, that 350pH ESL is 879 mOhms!
Through the wonders of series resonance, we can use a 470pF NPO
capacitor with a (measured) 140 mOhm ESR to apply a 140 mOhm resistance
across the power planes at 392MHz, even though the impedance of the ESL
is 879mOhms. This particular capacitor has a Q of 6.3, so I would
classify it as a very low ESR capacitor. But it can be useful against
a 400 MHz EMI problem frequency if it is precisely located on the power
planes.
You have to have software tools to place capacitors of this frequency
in effective positions. Several such capacitors may bring the impedance
down below 50 mOhms, but things get really tricky at these frequencies
and impedances. Also, capacitors with a Q this high can cause
impedance peaks at slightly higher and lower frequencies. (This is
playing with fire and you can get burned...) We have been successful
at obtaining a measured 6 mOhms at 600MHz by using capacitors on power
planes, but I question whether that was really necessary to make a
successful product.
A far better solution is to use the impedance of closely spaced power
planes to decouple above several hundred MHz. Consider the following
table of FR4 (dK=4) power plane characteristics:
dielectric capacitance spreading impedance
thickness (pF/sq in) (pH/square) (mOhm-inch)
---------- ----------- ----------- ----------
4 mil 225 130 750
2 mil 450 65 325
1 mil 900 32 162
Even with 4 mils of separation between power planes, we get 225pF for
every square inch. Capacitance is inversely proportional to thickness
so we get much more capacitance as we cut the dielectric thickness in
half and then cut it in half again.
But even more important than that, the spreading inductance of the
power planes drops from 130 pH per square to 65 and then 32 pH per
square as the dielectric gets thinner. The spreading inductance alone
on 4 mil power planes is very comparable to the ESL of the best mounted
capacitors. There is no point in placing a bunch of low ESL capacitors
on a pair of power planes unless the spreading inductance of the
planes is well below the parallel inductance of the capacitors.
An even better figure of merit for the power planes is the impedance.
A one inch wide strip of 4 mil power plane material has 750 mOhms of
impedance. At high frequencies (frequency where the lateral distance
on a PCB is not negligible compared to the wavelength) the power plane
impedance becomes very important. There is no point in paralleling a
bunch of low ESR, low ESL capacitors together to hit a 10 mOhm target
impedance if the power plane impedance that connects the capacitors to
the power consumers (uP, ASICs) is higher than the capacitors. It's
like trying to supply the city's water through a garden hose.
The short answer to your question is that above several hundred MHz,
the power planes are not only sufficient for decoupling, but absolutely
necessary for it. There are several companies that are beginning to
provide power plane material that is 1 mil or thinner (i.e. Dupont and
3M). The trick is learning how to incorporate this material into PCBs
and electronic packages. I believe this is the key to low impedance
power distribution in the GHz range.
BTW, there is a paper out on the si web site that describes power plane
modeling and simulation results. An extension to this paper will be
published in the August 2001 IEEE Transactions on Advanced Packainging
that defines and discusses spreading inductance (if I can get the final
edits in on time...).
http://www.qsl.net/wb6tpu/si_documents/docs.html
There is also a paper that talks about a distributed model for discrete
capacitors. That paper contains some information on how to measure the
performance of capacitors mounted on power planes. It is temporarily
located at
http://groups.yahoo.com/group/si-list/files/Published%20SI%20Papers%20from%20Sun/
regards,
Larry Smith
Sun Microsystems
> Delivered-To: si-list@xxxxxxxxxxxxxx
> From: Larry Miller <ldmiller@xxxxxxxxxxxxxxxxxxxx>
> To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
> Subject: [SI-LIST] Re: decoupling
> Date: Wed, 11 Jul 2001 09:47:56 -0700
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>
>
> Above 250 MHz my experience is that the plane capacitance (and no doubt the
> die capacitance in the chips) is the only capacitance still working well.
> The surface-mount discretes have largely gone to inductors, at least for the
> low impedances (<1-5 ohms) needed for bypassing.
>
> However, there may be some special packages coming out or newly available
> that extend the range of discretes by cleverly cancelling the package
> inductance. I haven't tried any of those yet.
>
> Larry Miller
>
> -----Original Message-----
> From: Khalid Ansari [mailto:khalida@xxxxxxxxxxx]
> Sent: Wednesday, July 11, 2001 9:19 AM
> To: si-list@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: decoupling
>
>
>
> Larry,
>
> What happens much above 250 MHz, do we need any more
> capacitors or is the power to ground plane capacitance
> sufficient?
>
> >470 pF 232 MHz
> >0.01 uF 50 MHz
> >0.1 uF 16 MHz
>
> >Putting low ESR capacitors in parallel is like playing with fire. You
> >can cook with fire and heat your house, but if you are not careful with
> >fire, you will get burned. I am a strong advocate of multiple low ESR
> >capacitors in parallel because I believe we have learned how to make
> >good, safe use of them. The optimum power distribution system (fewest
> >components, least cost, least complexity) is obtained from careful
> >selection and placement of capacitors with a reasonably high Q (low ESR).
> >
> >The trick is to create a low and flat impedance profile in the
> >frequency domain by using different valued capacitors in parallel.
> >Systems behave best when chips look out and see a power distribution
> >system that is resistive in phase (flat impedance). We like to
> >establish a target impedance which is defined as
> >
> >
> >Ztarget = power_supply_voltage * 5% / transient_current.
> >
> >If your PDS impedance meets the target impedance up to the highest
> >frequency of interest, your noise will be within acceptable limits.
> >Much more is written on this topic in
> >
> >"Power Distribution System Design Methodology and Capacitor
> >Selection for Modern CMOS Technology"
> >
> >http://www.qsl.net/wb6tpu/si_documents/docs.html
> >
> >It is easy to meet a 1 Ohm or 0.1 Ohm target impedance using "rules of
> >thumb" for decoupling and high ESR capacitors. It becomes a little
> >more difficult to meet a 10 mOhm target. If you are trying to meet 1
> >mOhm target impedance up to several hundred MHz, it will be very
> >difficult unless you have a well defined methodology and some software
> >tools to help you. On some of our more recent products, at least one
> >of each of the ceramic capacitors from the following menu are used:
> >
> >100uF,
> >47uF, 22uF, 10uF,
> >4.7uF, 2.2uF, 1uF,
> >470nF, 220nF, 100nF,
> >47nF, 22nF, 10nF,
> >4.7nF, 2.2nF, 1nF,
> >680pF, 470pF, 330pF, 220pF, 150pF, 100pF
> >
> >With three capacitors per decade of capacitance, it is possible to make
> >a flat impedance vs frequency profile from about 200 kHz to 400 MHz
> >without any problem from parallel antiresonances. The lower the ESL
> >and ESR (within reason), the fewer components you need. X7R capacitors
> >tend to have Q's between 2 and 5 and three values per decade are
> >sufficient. NPO (COG) capacitors may have Q's between 5 and 10 and six
> >values per decade are useful. Closely spaced power planes may be used
> >instead of some of the pF capacitors.
> >
> >We have our own internal software tools to help manage the design.
> >Cadence is marketing the Power Delivery Tool under SpectraQuest that
> >does the same thing as our tools. The Cadence tool is even better
> >because it is hooked up to the design data base for the PCB.
> >
> >Like all SI tools, these tools are based on models and the analysis is
> >only as good as the models. These days, I spend half of my life out in
> >the lab measuring capacitors and reducing the measured data. The
> >capacitor vendors could help me greatly by measuring the ESR and ESL of
> >their capacitors and publishing the data. They could also help by
> >designing capacitors that have the absolute minimum internal
> >inductance. BTW, traditional measurement techniques do not obtain very
> >good values for ESR and ESL. (Maybe that should be the topic of
> >another email.)
> >
> >regards,
> >Larry Smith
> >Sun Microsystems
>
>
>
>
>
>
>
>
>
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