[SI-LIST] Re: decoupling

  • From: Larry Smith <ldsmith@xxxxxxxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Fri, 13 Jul 2001 17:40:48 -0700 (PDT)

Brad - Thanks for noticing that the chip/package resonance paper is out
there.  I was supposed to have presented it in Hawaii this week, but
travel restrictions prevailed...  Anyway, it is now in the public
domain.

Yes, the chip/package resonance frequency was around 35 MHz on a recent
product.  For the last 15 years, the chip/package resonant frequency
has been somewhat under 100 MHz.  I worked on a product in 1988 where
it was about 80 MHz.  The inductance was about 1 nH, so by my favorite
formula, f0 = 1/{2pi*sqrt(LC)}, the capacitance in the chip must
have been about 4 nF.

Since then, the capacitance keeps going up and the inductance keeps
going down, leaving the product almost constant.  For the product
analyzed in the paper, the capacitance is about 100X what it was in
1988.  We tried very hard to reduce the inductance, but it is not
1/100th of a nH.  I guess we have some more work to do..  That is why
the resonant frequency was just 35 MHz.

Decoupling capacitors at the PCB level have very little effect on the
chip/package resonant frequency, that is a property of the chip and
package.  Most chip people assume that there is an "ideal" power supply
hooked to the bottom of their chip on the PCB (little do they
know...).  If the impedance of the PCB power planes happens to be
inductive at chip/package resonant frequency, the  inductance is
increased and the frequency drops slightly further.  But more
importantly, the Q of the circuit ( omega*L/R ) increases, a very bad
thing.

Probably the best thing a PCB power distribution designer can do is
provide a resistive impedance (at the target impedance) up to more than
twice the chip/package resonant frequency (70 MHz in this case).  A
resistive impedance is much better than an inductive impedance.  Notice
that a resistive impedance decreases the Q of the circuit but an
inductive impedance increases it.  The other day, I commented that
systems behave better when the PDS impedance is resistive in phase.
This is why.  High Q for the chip/package resonance is very detrimental
to chip performance as explained in the paper.  One more time, that
reference is http://groups.yahoo.com/group/si-list/files/

I suppose it would be even better to provide a capacitive impedance
throughout the chip/package resonant frequency range.  But our target
impedance is already down at the 4 mOhm range.  It is possible to
provide a resistive impedance through the use of low ESR capacitors or
many high ESR capacitors in parallel.  But a capacitive impedance at
that frequency would require very low ESR capacitors with very low
ESL.  I think it is probably more practical to reduce the Q with
resistance than to increase the frequency with capacitance. 

regards,
Larry Smith
Sun Microsystems

> 
> Larry and all,
> 
> While downloading the papers you provided below I also downloaded the
> "Chip-Package Resonance in Core Power Supply Structures for a High Power
> Microprocessor" paper linked on the same webpage. Very interesting work,
> sorry I missed the Hawaii conference! I was surprised by the resonant
> frequency of ~35 MHz reported in this paper for what appears to be a P/BGA
> packaged device. I would have expected this to be higher. I would be
> interested in your, and others, comments on the effect decoupling capacitors
> would have on this resonance frequency. Has any of your work looked into
> this aspect? I would expect smaller caps which would be located very close
> to power supply pins of the device to remain capacitive at this frequency.
> This capacitance along with the plane capacitance should have the effect of
> increasing the resonant freq and dominating the effect of the resonant peak.
> However, caps that have effectively become inductive in this range add
> parallel inductance to the equivalent circuit, thereby lowering the resonant
> freq and increasing the peak impedance (not good!). Thus, good decoupling
> cap selection and placement should reduce the effect package resonance has
> on the power system. Comments?
> 
> Regards,
> Brad Crowell
> AMIRIX Systems

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