[SI-LIST] Re: IC Receiver Design for Low Jitter
- From: "ABOULHOUDA,SAMIR (A-England,ex1)" <samir_aboulhouda@xxxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 13 Jul 2001 19:01:08 +0200
Bonjour,
I second your comment on the utility of performing a frequency domain
analysis.
Would you please elaborate your thoughts on that: what kind of analysis are
you thinking about:
- PSRR?
- S-parameters? (we have to ask ourselves about the validity of this kind of
analysis if we deal with Digital ICs or/and strong Non-linear devices).
- ??= Any other analysis I didn't think about it yet.
Thanks,
Samir
-----Original Message-----
From: D. C. Sessions [mailto:dcs@xxxxxxxxxxxxxxxx]
Sent: Friday, July 13, 2001 5:42 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IC Receiver Design for Low Jitter
[cut]
That said, I've been a bit surprised at how few CMOS I/O designers
do any frequency-domain analysis. It's been a non-issue for long
enough that the practice has been forgotten or something, but from
some of my own experiences it's heading for front-burner status again.
I'd suggest asking your ASIC house for AC stability data (don't forget
to check for sensitivity completeness) on any high-performance I/Os
that you're considering. (Yes, that's a subtle plug.)
[cut]
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