[SI-LIST] Re: IC Receiver Design for Low Jitter
- From: jim freeman <kacief@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 13 Jul 2001 10:19:59 -0700
Hi DC,
When did you move to lumbercartel or is that just a pseudonym.
Thanks
Jim Freeman
"D. C. Sessions" wrote:
> On Friday 13 July 2001 08:44, you wrote:
>
> > I have a question that some IC design guru could help with. The issue is
> > how much additional random jitter is added to an incoming signal by the
> > receiver. Let's assume the receiver is driven well beyond threshold, so
> > incoming signal strength is not an issue. Further, the signalling is
> > discrete binary amplitude (digital).
>
> The dominant random jitter contribution in the receiver is from supply and
> substrate noise. Supply noise is pretty easy to both control and to
> model, but substrate noise is something of a black art for the time being.
>
> > When such a circuit is done at the PCB level by an RF designer, a stability
> > analysis is done to ensure there is no gain peaking or marginally stable
> > behavior of the circuit. Any noise generated by devices in the circuit is
> > magnified by gain peaking resulting from unintentional feedback. This
> > feedback can occur within the devices themselves and depends on the
> > reflections and matching within the circuit. An extreme case of a
> > marginally stable condition can cause brief periods of oscillation as the
> > signal transitions, making the exact timing of the edge more uncertain,
> > thus adding jitter.
>
> On-chip we're generally operating at much lower Q than on-board.
> This usually results in great frustration, but occasionally someone like
> you reminds us that it's not all bad.
>
> > When considering this situation for IC design the situation becomes
> > unclear. I've discussed methodologies with analog ASIC designers. The
> > tools used are some form of Spice. None of the designers mentioned any
> > consideration of stability. If the instability in the circuit is at a very
> > high frequency, Spice may not reveal it due to the finite time step
> > duration. Is there a concern in the IC design case?
>
> As a rule, the timesteps are both dynamic (shorter steps when things are
> happening) and much, much shorter than the Ft of the active devices.
> In other words, for frequencies that present any kind of modeling issue
> the gain is long, long gone.
>
> That said, I've been a bit surprised at how few CMOS I/O designers
> do any frequency-domain analysis. It's been a non-issue for long
> enough that the practice has been forgotten or something, but from
> some of my own experiences it's heading for front-burner status again.
> I'd suggest asking your ASIC house for AC stability data (don't forget
> to check for sensitivity completeness) on any high-performance I/Os
> that you're considering. (Yes, that's a subtle plug.)
>
> --
> | I'm old enough that I don't have to pretend to be grown up.|
> +----------- D. C. Sessions <dcs@xxxxxxxxxxxxxxxx> ----------+
>
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