[SI-LIST] Re: decoupling
- From: Zhiping Yang <zhiping@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 19 Jul 2001 10:46:52 -0700
Hi,
Here is my $0.02 input.
Where to put the decoupling caps is a complicated problem.
The PCB stackup is a big factor to consider. No matter where
you put it, the goal is to minimize the total loop inductance
between IC and caps.
Here is what I would recommend:
1. If you can place IC and caps pretty near each other, then
placing them on the same side is better than the opposite side.
2. If IC and caps are on the same side and the power layer is near IC,
then it's better to place cap near GND pin. If the ground layer is
near IC, then it is better to place cap near power pin. Here is a plot
of suggested placement
- IC - -cap-
| | | |
--*----------*------- GND
| |
------*--*-----------PWR
3. I would recommend to connect IC and cap PWR/GND pins directly
to PWR/GND layer through vias.
Thanks.
johnni.friis@xxxxxxxxx wrote:
> Hi folks
>
> Where do you place the caps ?
> The caps and the IC is on the side of the PCB, or ?
>
> 1. Close to Vcc pin
> The GND connection of the IC and the cap are made directly to GND-plane=
> .
> The Vcc connection is made from Vcc pin to cap to via plane. (See below=
> ).
>
> ___
> Vcc pin o-----| |----o via to Vcc plane
> |cap|
> |___|-----o via to Gnd plane
>
> 2. Close to GND pin
> The Vcc connection of the IC and the cap are made directly to Vcc-plane=
> .
> The GND connection is made from GND pin to cap to via to plane. (See
> below).
>
> ___
> Gnd pin o-----| |----o via to Gnd plane
> |cap|
> |___|-----o via to Vcc plane
>
> Some say 2 is best. The current from cap to IC will generate a noise
> voltage in the plane (1. in GND-plane and 2. in Vcc-plane).
> It's best to have the noise in Vcc-plane.
> (Our baords is 4 layers, plane seperation of 1 mm (40 mill), F=3D40 M=
> Hz,
> singel ended signals, tr/tf ~ 1nS. )
> What do you think ?
>
> Best regards,
>
> Johnni Friis
> G=E5sdal Bygningsindustri A/S
> Decoration & Sunscreening, Electrics and Shutters
> B=E6kg=E5rdsvej 40
> DK 6900 Skjern
> E-mail: johnni.friis@xxxxxxxxx
> Phone +45 9980 6666
> Fax +45 9980 6260=
>
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--
Zhiping Yang, Ph. D.
Hardware Engineer
Cisco Systems
270 West Tasman Drive
Mail Stop:SJCG/2/2
San Jose, CA 95134 | |
email: zhiping@xxxxxxxxx :|: :|:
Tel : 408 525 5690 :|||: :|||:
Fax : 408 526 5504 .:|||||||:..:|||||||:.
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