[SI-LIST] Re: Placement of decoupling capacitors

  • From: Ray Anderson <Raymond.Anderson@xxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 31 Jul 2001 14:53:02 -0700 (PDT)

Khalid Ansari wrote:
>
>I just have enough space to place this one close to the pin, the rest have
>to go quite further away due to space constraint.  Placing them too far
>away I have to worry about the loop inductance.
>

        The loop inductance you need to be concerned with is
        that of the loop formed by the decap, the mounting pads,
        vias and power planes. The distance between the decap
        and the IC doesn't determine the loop inductance.
        
        That being said, the distance IS an issue when you consider
        the time of flight between the decap and the IC consuming
        the current. A commonly used rule-of-thumb is that
        the decap should be within 1/10 wavelength (at the frequency
        of interest) of the chip it is supplying in order to be effective.  
        If you are too far away, the chip requiring the current may not 
        get it in time from the decap sourcing the current.
        
-Ray Anderson
Sun Microsystems Inc.
        
        

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: