[SI-LIST] Re: On-chip Terminations
- From: "D. C. Sessions" <si-list@xxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 13 Jul 2001 09:33:16 -0700
On Friday 13 July 2001 08:13, you wrote:
> Greetings,
> I recently read a brief paper on Xilinx's XCITE technology.
>
> The only problem is I couldn't find any tolerance values for these on-chip
> resistors.
>
> Discrete resistors have a 1% tolerance.
> Buried resistors have a 10-15% tolerance.
> On-chip resistors have a ??? tolerance.
>
> Does anybody have a "ball-park" number on this?
Depends on whether the process controls for sheet resistance.
If the fab maintains sheet resistance controls, you can see tolerances
in the 10% range. If not, 20-25% is more like it.
You'll never see uncontrolled 1% tolerances in standard processes
because polysilicon has a high tempco and the other resistor-definition
mechanisms have high physical definition tolerances.
All of which is somewhat moot because active compensation for
PVT is pretty easy. Admittedly, it's easier for narrow common-mode
ranges (which is one of the reasons that SLVS uses ground termination,
although not the major one.)
--
| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat. |
+--------------- D. C. Sessions <dcs@xxxxxxxxxxxxxxxx> --------------+
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