[SI-LIST] Re: LVDS Glitch Problem
- From: "S. Weir" <weirsp@xxxxxxxxxx>
- To: Paul.Denomme@xxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 26 Jul 2001 08:27:14 -0700
Paul,
One other consideration, what is the situation with aggressor signals?
Regards,
Steve.
At 09:48 AM 7/26/01 -0400, Denomme, Paul S. wrote:
>I am trying to solve a problem for someone that is having a glitch with
>their LVDS clock line. They are experiencing false triggering from their
>622MHz clock line.
>Here is the setup:
>
>There are 2 boards. I will refer to them as Board 1 and Board 2.
>Board 1 has a differential impedance of 100 ohms and the diff trace length
>of 4.5 inches.
>Board 2 has a differential impedance of 84 ohms and the diff trace length of
>1.5 inches.
>The signal is driven from board 1 and recieved on Board 2 where it is also
>terminated by 100 ohms between the paired signals.
>The interface between board 1 and board 2 is a high density low profile
>connector.
>The LVDS signal is 622 MHz with 300 pSec. rise times.
>The trace lengths between the diff. pairs on both boards are matched.
>
>My first impression regarding this setup is there is a large discontinuity
>between Board 1 and Board 2. I believe they are experiencing a resonance on
>the output of the LVDS that seems to have a frequency of approximately 500
>psec., which is approx. the round trip time of the signal on board 2 (540
>psec.)for the 300 psec. rise time.
>
>My questions to all of you is:
>
> Would this impedance discontinuity between board 1 and board 2 be
>enough to cause false triggering in their LVDS clock line? Anyone have any
>experience trouble shooting a similar problem?
>
>Granted the impedance discontinuity is not desirable and needs to be revised
>for their next run of the boards, but I am trying to determine whether
>changing this impedance will be enough so they will eliminate the false
>triggering.
>
>
>Thank you in advance for your reply,
>
>Paul Denomme
>
>
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