[SI-LIST] Re: ADDITIONAL PCI CLOCKS
- From: "Volk, Andrew M" <andrew.m.volk@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 11 Jul 2001 15:37:00 -0700
Watch out when shorting clock drivers together. Some manufacturers put a
skew between groups of output to minimize switching noise. If you tie the
skewed outputs together, there will be a large totem-pole current that will
cause more noise and jitter on the outputs. Check with your clock generator
vendor.
Andrew Volk
Intel Corp.
-----Original Message-----
From: Beal, Weston [mailto:weston_beal@xxxxxxxxxxx]
Sent: Wednesday, July 11, 2001 2:33 PM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: ADDITIONAL PCI CLOCKS
Chandan,
tie all the drivers together at one point and then split them out through
series resistors to each receiver. This will minimize the skew caused by
different loads on the nets. You should also simulate the nets to account
for the different loading effects of different devices.
Regards,
Weston
-----Original Message-----
From: Chandan [mailto:chandan_career@xxxxxxxxx]
Sent: Tuesday, July 10, 2001 4:10 AM
To: SI FORUM
Subject: [SI-LIST] ADDITIONAL PCI CLOCKS
Hi,
My clock synthesizer provides 6 PCI (33MHz) clocks,
but I am in need of 8.
Apart from using a different clock synthesizer, does
anyone out there have other solutions to my
problem?
I thought of using one of the PCI outputs of the
synthesizer to drive two PCI devices as follows:
The output will be given to a resistor (value equals
half the line's characteristic impedance minus the
driver's source impedance). The other end of this
resistor will then be split into two traces that are
routed to the individual PCI devices.
Note that all traces will have the same value of
characteristic impedance (60 ohms). The clock
driver can source 22mA and sink 25mA.
Articles on transmission lines speak of this method.
Has anyone tried this on a PCI bus? Is there
something I ought to care of?
Thanks,
Chandan
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