[SI-LIST] Re: decoupling
- From: e <evillaf@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 11 Jul 2001 20:39:00 -0700
Steve,
In a popular power supply 'filtering' application, a pi structure is used with
capacitors on both sides of a ferrite bead. Does this configuration suffer from
power supply choking, assuming the cap on the load side provides sufficient
charge for the load during switching, and that it re-charges adequately during
non-switching times?
Thanks in advance.
Ellis
"S. Weir" wrote:
> Michael,
>
> The device switching currents are fed by the board power system. If you
> insert an impedance, you are choking the power supply and the on-chip
> voltage rail drops. That is a very bad thing.
>
> Regards,
>
> Steve.
> At 05:27 PM 7/11/01 -0500, you wrote:
>
> >Can you explain why adding ferrite bead in series with a power lead is a
> >bad thing? Thanks.
> >
> >Regards,
> >Michael Chan
> >
> >
> >-----Original Message-----
> >From: Ritchey Lee [mailto:leeritchey@xxxxxxxxxxxxx]
> >Sent: Wednesday, July 11, 2001 4:48 PM
> >To: si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: decoupling
> >
> >
> >
> >Yes, at 250 MHz and up, the plane capacitor is the work horse. Imagine what
> >happens when someone tells you to insert a ferrite bead in series with a
> >power
> >lead, isolating it from the plane capacitor. Really bad things! Sadly,
> >many
> >applications notes tell you to do this, as do some of the less well trained
> >EMI
> >people. I spend a lot of time fixing designs that have followed this
> >advice.
> >
> >Lee
> >
> >Khalid Ansari wrote:
> >
> > > Larry,
> > >
> > > What happens much above 250 MHz, do we need any more
> > > capacitors or is the power to ground plane capacitance
> > > sufficient?
> > >
> > > >470 pF 232 MHz
> > > >0.01 uF 50 MHz
> > > >0.1 uF 16 MHz
> > >
> > > >Putting low ESR capacitors in parallel is like playing with fire. You
> > > >can cook with fire and heat your house, but if you are not careful with
> > > >fire, you will get burned. I am a strong advocate of multiple low ESR
> > > >capacitors in parallel because I believe we have learned how to make
> > > >good, safe use of them. The optimum power distribution system (fewest
> > > >components, least cost, least complexity) is obtained from careful
> > > >selection and placement of capacitors with a reasonably high Q (low
> >ESR).
> > > >
> > > >The trick is to create a low and flat impedance profile in the
> > > >frequency domain by using different valued capacitors in parallel.
> > > >Systems behave best when chips look out and see a power distribution
> > > >system that is resistive in phase (flat impedance). We like to
> > > >establish a target impedance which is defined as
> > > >
> > > >
> > > >Ztarget = power_supply_voltage * 5% / transient_current.
> > > >
> > > >If your PDS impedance meets the target impedance up to the highest
> > > >frequency of interest, your noise will be within acceptable limits.
> > > >Much more is written on this topic in
> > > >
> > > >"Power Distribution System Design Methodology and Capacitor
> > > >Selection for Modern CMOS Technology"
> > > >
> > > >http://www.qsl.net/wb6tpu/si_documents/docs.html
> > > >
> > > >It is easy to meet a 1 Ohm or 0.1 Ohm target impedance using "rules of
> > > >thumb" for decoupling and high ESR capacitors. It becomes a little
> > > >more difficult to meet a 10 mOhm target. If you are trying to meet 1
> > > >mOhm target impedance up to several hundred MHz, it will be very
> > > >difficult unless you have a well defined methodology and some software
> > > >tools to help you. On some of our more recent products, at least one
> > > >of each of the ceramic capacitors from the following menu are used:
> > > >
> > > >100uF,
> > > >47uF, 22uF, 10uF,
> > > >4.7uF, 2.2uF, 1uF,
> > > >470nF, 220nF, 100nF,
> > > >47nF, 22nF, 10nF,
> > > >4.7nF, 2.2nF, 1nF,
> > > >680pF, 470pF, 330pF, 220pF, 150pF, 100pF
> > > >
> > > >With three capacitors per decade of capacitance, it is possible to make
> > > >a flat impedance vs frequency profile from about 200 kHz to 400 MHz
> > > >without any problem from parallel antiresonances. The lower the ESL
> > > >and ESR (within reason), the fewer components you need. X7R capacitors
> > > >tend to have Q's between 2 and 5 and three values per decade are
> > > >sufficient. NPO (COG) capacitors may have Q's between 5 and 10 and six
> > > >values per decade are useful. Closely spaced power planes may be used
> > > >instead of some of the pF capacitors.
> > > >
> > > >We have our own internal software tools to help manage the design.
> > > >Cadence is marketing the Power Delivery Tool under SpectraQuest that
> > > >does the same thing as our tools. The Cadence tool is even better
> > > >because it is hooked up to the design data base for the PCB.
> > > >
> > > >Like all SI tools, these tools are based on models and the analysis is
> > > >only as good as the models. These days, I spend half of my life out in
> > > >the lab measuring capacitors and reducing the measured data. The
> > > >capacitor vendors could help me greatly by measuring the ESR and ESL of
> > > >their capacitors and publishing the data. They could also help by
> > > >designing capacitors that have the absolute minimum internal
> > > >inductance. BTW, traditional measurement techniques do not obtain very
> > > >good values for ESR and ESL. (Maybe that should be the topic of
> > > >another email.)
> > > >
> > > >regards,
> > > >Larry Smith
> > > >Sun Microsystems
> > >
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