[SI-LIST] Re: decoupling
- From: Wang Xiao-yun <wangxiaoyun@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 20 Jul 2001 10:07:49 +0800
Hello ZhiPing:
I'm not clear on the comments that placing the capacitors on the same=20
side of the component would be better. Here is my understanding:
1. If the decoupling capacitor is placed on the same side, the distance=20
between the component and the capacitor will have to satisfy the clearance=
=20
defined in DFM rule. In normal cases, the clearance is much larger than the=
=20
escape length (component pwr/gnd pin) + escape length (capacitor)
2. For BGA and alike, the pwr/gnd balls in inner ring should be escaped=20
immediately to pwr/gnd layer. The corresponding capacitors can only achieve=
=20
the shortes impedance path to the balls when placed on the opposite side.
3. Given that most of the PCBs are constructed in a symmetrical way (the=20
distances of paired pwr/gnd layers to the top and bottom side are same),=20
the effective lengths of through hole vias to the pwr/gnd layers don't have=
=20
much difference no matter which side the capacitor is placed.
I appreciate comments from you and other gurus.
Best regards.
At 10:46 01-7-19 -0700, you wrote:
>Hi,
>
>Here is my $0.02 input.
>
>Where to put the decoupling caps is a complicated problem.
>The PCB stackup is a big factor to consider. No matter where
>you put it, the goal is to minimize the total loop inductance
>between IC and caps.
>
>Here is what I would recommend:
>1. If you can place IC and caps pretty near each other, then
>placing them on the same side is better than the opposite side.
>2. If IC and caps are on the same side and the power layer is near IC,
>then it's better to place cap near GND pin. If the ground layer is
>near IC, then it is better to place cap near power pin. Here is a plot
>of suggested placement
>
> - IC - -cap-
> | | | |
>--*----------*------- GND
> | |
>------*--*-----------PWR
>
>3. I would recommend to connect IC and cap PWR/GND pins directly
>to PWR/GND layer through vias.
>
>Thanks.
>
>
>
>johnni.friis@xxxxxxxxx wrote:
>
> > Hi folks
> >
> > Where do you place the caps ?
> > The caps and the IC is on the side of the PCB, or ?
> >
> > 1. Close to Vcc pin
> > The GND connection of the IC and the cap are made directly to GND-plane=
=3D
> > .
> > The Vcc connection is made from Vcc pin to cap to via plane. (See below=
=3D
> > ).
> >
> > ___
> > Vcc pin o-----| |----o via to Vcc plane
> > |cap|
> > |___|-----o via to Gnd plane
> >
> > 2. Close to GND pin
> > The Vcc connection of the IC and the cap are made directly to Vcc-plane=
=3D
> > .
> > The GND connection is made from GND pin to cap to via to plane. (See
> > below).
> >
> > ___
> > Gnd pin o-----| |----o via to Gnd plane
> > |cap|
> > |___|-----o via to Vcc plane
> >
> > Some say 2 is best. The current from cap to IC will generate a noise
> > voltage in the plane (1. in GND-plane and 2. in Vcc-plane).
> > It's best to have the noise in Vcc-plane.
> > (Our baords is 4 layers, plane seperation of 1 mm (40 mill), F=3D3D40=
M=3D
> > Hz,
> > singel ended signals, tr/tf ~ 1nS. )
> > What do you think ?
> >
> > Best regards,
> >
> > Johnni Friis
> > G=3DE5sdal Bygningsindustri A/S
> > Decoration & Sunscreening, Electrics and Shutters
> > B=3DE6kg=3DE5rdsvej 40
> > DK 6900 Skjern
> > E-mail: johnni.friis@xxxxxxxxx
> > Phone +45 9980 6666
> > Fax +45 9980 6260=3D
> >
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>
>--
> Zhiping Yang, Ph. D.
> Hardware Engineer
> Cisco Systems
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--
Wang Xiao-yun
Shanghai, China, http://go.163.com/philharmania
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