[SI-LIST] Mictor probes and 'high' speed/sensitive signals
- From: S Tatlow <s_tatlow@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 20 Jul 2001 02:11:42 +0100 (BST)
Hi people,
I am a PCB layouter, and I have a question or 2
regarding the effects of Mictor logic analyser probes
on 'high' speed (133MHz DDRAM buses/clocks) or
sensitive signals (MOST TX/RX). I guess these probes
are exactly intended for this sort of work, but
thought I would pose the following questions anyway,
as I am not sure:
1. I have placed the probe connectors at the end of
the 'line' on daisy chained signals, as I have pretty
much no chance of placing them always somewhere along
the line, without requiring either extra layers, or
super-long tracks. Does this produce any negative
effects, with respect to antennae, reflections, etc.?
What kind of difference does the system see between
the case of probes attached, and not attached? How
about for some of the particularly sensitive signals
(e.g. MOST TX/RX), which only have a load and source,
connected by a short (10-15mm) track, plus the Mictor
pin (extra length maybe 50mm!)? My problem is, that
with over 30 pins per Mictor probe, it is often
impossible to position the probe connector, so that
the extra length added by the connections to the
Mictor probe is negligble in all cases, and in some
cases, it might add quite a few inches ...
2. In the case of the DDRAM buses, I have an extra
problem: the 133 MHz clock rate is nothing new to me,
and no real cause for concern. That is, until the
connections to the Mictor probes are thrown into the
equation, with respect to choosing a workable layer
stacking. I can see that I can route all but the
Mictor connections pretty much ideally on the layers
1,3,6,8 using the following stack-up:
L1 Top
L2 GND
L3 Signal 1
L4 3V3
L5 1V8, 2V5, 5V
L6 Signal 2
L7 GND
L8 Bottom
I think this gives me the best chance of keeping
impedances reasonably constant, and avoiding any of
the dreaded cut-in-the-plane problems by keeping ALL
signal layers referenced to a solid GND plane (this is
true, even for L6, right?). However, to route the
Mictor connections, I have to either:
a. add 2 more layers :-(
b. use the 3V3 plane in the DDRAM area, where this
supply is not needed.
Cost-wise, I would like to use option b, but am
worried that this may cause problems - that is, I
guess, high speed signals switching from a
GND-referenced signal layer, to the 2V5 plane (any
other problems?), although I do have plenty of
decouplers in this area.
Address and clock lines between BGA and 4 DDRAM chips
are all on only L3 or L6, with line lengths inc.
Mictor of about 5 inches, and data lines to each
individual chip are worst case 2 inches plus 2 inches
extra to Mictor probes, and would be routed on either
L1+L4 or L8+L4, with the L4 sections crossing
perpendicular to the Address lines on L3.
I think and hope that I am worrying too much for
signals at this speed and these lengths (although
would an increase in speed, for example, to 200MHz
make a difference, in this case?), but I thought I
would tap you people for your thoughts anyway, plus
any other hints with regards to these Mictor probes
(for example, how does it affect clock line
termination?), which are relatively new to me.
Apologies for the 'novel' and thanks in advance for
any guidance you can offer!
Sol
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