[SI-LIST] Re: decoupling
- From: "Grossman, Brett" <brett.grossman@xxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 12 Jul 2001 15:46:44 -0700
Been detached for a while as I relocated to a new state that for the time
being has power all the time, but is somewhat low on water.
I haven't been following this entire thread, and may have missed the essence
of the discussion, but I assume that it is more specifically targeting
CPU's and high power ASIC's with relatively complex ceramic or organic
package substrates, large currents with transient event times on the order
of > ~0.5 nS. If I understand the arguments it seems these devices would
need boatloads of localized on device decoupling to manage transient
activity at > 100 MHz?
Curious if this same methodology would apply to something like a Sonet TIA
in a CSP, or a RF PA in a flip-chip package? In designs utilizing these
devices I generally see fairly small value components on the order of 100's
of pF utilized for on-board decoupling. To a first order I would imagine it
is intended to provide power decoupling at frequencies that could exceed
100MHz, but I could be completely off my rocker.
Any comments welcome.
-Brett
I find the water shortage issue somewhat perplexing as I had been told it
rains all the time in Oregon. As an interesting bit of trivia I recently
discovered a rainfall map of US the for the summer months that showed Oregon
having on the order of 10" of rain between May 1st and October 1st.
Conversely my home state of Minnesota receives about 2.5-3 times that amount
in the same period. I guess 'rains all the time' like many things is matter
of perspective?
-----Original Message-----
From: Chris Cheng [mailto:chris.cheng@xxxxxxxxxxxx]
Sent: Thursday, July 12, 2001 12:36 PM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: decoupling
believe me i have the best &^%$* package. you are confusing signal traces
that have pf of loading and 1nh of inductance with core that has uf's of
loading and ph's of inductance. orders of magnitude difference in resonance.
i have done a few ghz processes with >100W power packaging with the best
flip chip substrate. you can put a million low impedance cap solder right
at the pin of the package and it won't make a &^%$* difference to the
core noise >100MHz. what ghz processes have you done ?
-----Original Message-----
From: Ed Priest [mailto:Ed_Priest@xxxxxxxxxxxxxx]
Sent: Thursday, July 12, 2001 10:09 AM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: decoupling
You can pass out a +ghz signal single endedly and if you think you can't get
> 100Mhz noise out of a package you are using some really &^%$* packages or
are using die that don't have >100Mhz switching activity. In a package with
coupled planes - the power planes look like transmission lines with
distributed poles and zeros. Good flip chip packages have very low impedance
between PCB and the die. I guarantee you can get high frequency noise down
to the PCB - I've help troubleshoot a lot of boards for people who thought
they couldn't. If you have a bunch of chips on a board with 400Mhz
switching, spending time lowering the impedance of your power distribution
at 400Mhz is time well spent.
Ed
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