[SI-LIST] AMD Forms Hyper-Transport I/O Consortium
- From: Jonathan Dowling <jdowlin2@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 24 Jul 2001 17:55:04 -0700 (PDT)
Gentle SI-LIST Readers,
It is with great pleasure that I announce to you the formation of
a new industry-wide consortium for promotion of AMD's high speed
link bus I/O technology. In my letter here, my wish would be
simply to present it to you all plain and unadorned, without any
embellishment of preface or uncountable muster of customary
sonnets, epigrams, and eulogies, such as are commonly put at the
beginning of pastoral works. But, I have been unable to
transgress the natural order of things, and must relate that
Hyper-Transport Technology is composed of a science of which
Aristotle never dreamt, nor St. Basil said a word, nor Cicero had
any knowledge; nor do the observations of astrology come within
the range of its fanciful vagaries; nor have refutations of the
arguments used in rhetoric anything to do with it; nor does it
mean to preach to anybody, mixing up things human and divine.
It has only to avail itself of truth to nature in its composition.
But, how could you expect us not to feel uneasy about what that
ancient lawgiver they call the Public will say when it sees us,
after slumbering so many years in the silence of oblivion, coming
out now with all our years upon our backs, without a story full
of maxims from Aristotle, and Plato, and the whole herd of
philosophers? In short, my friends, we are determined that
Hyper-Transport shall not remain buried in the designs of our
own, but that many of you will join the consortium, use HT in
your own designs, and help to garnish the HT specification with
all the things of which it currently stands in need.
AMD is forming a consortium to promote widespread development
of the Hyper-Transport (HT) bus architecture. Consortium members
will pay a fee to participate and are then free to implement the
technology royalty-free. A primary goal of the consortium is to
promote HT as an open standard. Regularly scheduled meetings
will commence this Fall. For more information, visit the URL at
http://www.hypertransport.org
Originally created as the next-generation I/O interface for AMD's
CPU and chipset products, HT is finding support in other
applications such as telecom/networking, embedded systems,
graphics, etc.
Hyper-Transport represents a dramatic departure from legacy PC
bus architecture in both the physical layer construction and in
the link protocol. HT supports a simultaneous bi-directional
dataflow through the use of 2 uni-directional channels per link.
Importantly, HT is a low latency bus that was designed to be
tester friendly. HT is specified currently to deliver a maximum
transfer rate of 1600MT/s over FR-4 PCB trace. The aggregate
bandwidth for a 16-bit X 16-bit link is 6.4GB/s.
This Fall the consortium discussion will focus on the current HT
specification, development of a connector/cabling infra-structure,
and other enabling activities. Going into next year, discussions
will begin on future development of HT. Internally, AMD has a
working proposal to double the transfer rate to 3200MT/s for the
next generation HT-II, but will defer to the group consensus
deliberated between consortium members in order to achieve the
most palatable PHY solution for HT-II.
The interconnect design of HT was originally fleshed out with the
Quad Design XTK tool suite and subsequently validated with Hspice
simulations of actual I/O designs. We have since ported the
'Spec' Quad XTK models to IBIS. Hopefully, the consortium will
generate healthy discussion regarding desired model formats.
Ultimately, the consortium will own the 'spec' model format(s)
and distribution thereof for HT.
As of now, AMD plans to release IBIS models for SI simulation, but
will consider customer demands for release in alternative formats.
E.g.(1) To date, AMD has never released Hspice models based on a
foundry process, but it will only happen in the future if
enough customers demand this format. (To boot, this may
involve a 3-way or possibly 4-way NDA between the various
parties involved.)
E.g.(2) To date, AMD has never released the APD files of package
designs for simulation, but it will only happen in the
future if enough customers demand this level of packaging
detail.
E.g.(3) AMD will only consider releasing ISF versions of the
Hammer CPU/chipset packages and supporting native XTK
models given customer requests to do so.
Cordially,
Jonathan Dowling
AMD
jonathan.dowling@xxxxxxx
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