Posts for si-list, 08-2002

Browse: Last Month: 07-2002 Main Archive Page Next Month: 09-2002

» [SI-LIST] September Meeting of RMCEMS Society and local EMC Class -
» [SI-LIST] General Trace Impedance -
» [SI-LIST] edge slope in eye diagram -
» [SI-LIST] Re: GTL buffers Vref -
» [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination -
» [SI-LIST] Re: GTL buffers Vref -
» [SI-LIST] Re: GTL buffers Vref -
» [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination -
» [SI-LIST] Re: GTL buffers Vref -
» [SI-LIST] GTL buffers Vref -
» [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination -
» [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination -
» [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination -
» [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination -
» [SI-LIST] Re: Measuring Power and Ground Plane Noise -
» [SI-LIST] SFF to SFP adapter board -
» [SI-LIST] Re: why eye crosspoint offset -
» [SI-LIST] Re: Ground plane split widths... -
» [SI-LIST] Re: Eye pattern generation in XTK -
» [SI-LIST] why eye crosspoint offset -
» [SI-LIST] Re: Measuring Power and Ground Plane Noise -
» [SI-LIST] Re: Measuring Power and Ground Plane Noise -
» [SI-LIST] Re: Measuring Power and Ground Plane Noise -
» [SI-LIST] Re: Measuring Power and Ground Plane Noise -
» [SI-LIST] Measuring Power and Ground Plane Noise -
» [SI-LIST] FDIP '02/EPEP '02 Reminder -
» [SI-LIST] Re: SONET Sync card -
» [SI-LIST] SONET Sync card -
» [SI-LIST] Looking for Chris Brewster -
» [SI-LIST] STM1 electrical -
» [SI-LIST] Re: Inter Symbol Interference -
» [SI-LIST] Re: Fw: Re: source synchronous constraint -
» [SI-LIST] Re: Inter Symbol Interference -
» [SI-LIST] Re: Dimensional stability after relamination -
» [SI-LIST] Re: source synchronous constraint -
» [SI-LIST] Re: Inter Symbol Interference -
» [SI-LIST] Re: FW: Transmission Line Model Tests -resend -
» [SI-LIST] Re: source synchronous constraint -
» [SI-LIST] Re: Fw: Re: source synchronous constraint -
» [SI-LIST] Inter Symbol Interference -
» [SI-LIST] Re: Quantization and Statistical Averaging -
» [SI-LIST] Re: Quantization and Statistical Averaging -
» [SI-LIST] Dimensional stability after relamination -
» [SI-LIST] Re: Quantization and Statistical Averaging -
» [SI-LIST] Fw: Re: source synchronous constraint -
» [SI-LIST] Re: source synchronous constraint -
» [SI-LIST] Re: source synchronous constraint -
» [SI-LIST] Re: source synchronous constraint -
» [SI-LIST] Re: source synchronous constraint -
» [SI-LIST] Re: source synchronous constraint -
» [SI-LIST] source synchronous constraint -
» [SI-LIST] Re: Damaging LVDS inputs (with embedded termination) using LVPECL voltage swings? -
» [SI-LIST] Re: Dude! You're simulating at Dell.... -
» [SI-LIST] Re: Damaging LVDS inputs (with embedded termination) using LVPECLvoltage swings? -
» [SI-LIST] Re: HSpice -
» [SI-LIST] Re: PCB Design Technique -
» [SI-LIST] Re: Damaging LVDS inputs (with embedded termination) using LVPECL voltage swings? -
» [SI-LIST] Damaging LVDS inputs (with embedded termination) using LVPECL voltage swings? -
» [SI-LIST] si-list repaired ! -
» [SI-LIST] Test Message for si-list debug -
» [SI-LIST] Attn. Mir Faiz Mohammad -
» [SI-LIST] HSpice -
» [SI-LIST] Re: Chip caps vs. Tantalum -
» [SI-LIST] Re: Chip caps vs. Tantalum -
» [SI-LIST] PCI Routing -
» [SI-LIST] AW: Re: DDR-II: SSTL_18 & ODT -
» [SI-LIST] Re: Chip caps vs. Tantalum -
» [SI-LIST] IPC_2251 draft copy - bulk capacitance query -
» [SI-LIST] Re: Package probe station vendors... -
» [SI-LIST] Re: Package probe station vendors... -
» [SI-LIST] Re: Chip caps vs. Tantalum -
» [SI-LIST] Re: DDR-II: SSTL_18 & ODT -
» [SI-LIST] Resume' posting to si-list -
» [SI-LIST] Re: Chip caps vs. Tantalum -
» [SI-LIST] What are the best available tools in market for Printed Circuit Board Level Signal Integrity Analysis -
» [SI-LIST] Require Work -
» [SI-LIST] Package probe station vendors... -
» [SI-LIST] Re: Clock-recovery for Dummies? -
» [SI-LIST] Re: Clock-recovery for Dummies? -
» [SI-LIST] Chip caps vs. Tantalum -
» [SI-LIST] Re: Clock-recovery for Dummies? -
» [SI-LIST] Re: Hspice error message? -
» [SI-LIST] Re: Hspice error message? -
» [SI-LIST] Re: One decoupling cap per BGA power pin? -
» [SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz -
» [SI-LIST] Scrambled clock -
» [SI-LIST] Hspice error message? -
» [SI-LIST] Re: One decoupling cap per BGA power pin? -
» [SI-LIST] Re: DDR-II: timing analysis -
» [SI-LIST] Re: Clock-recovery for Dummies? -
» [SI-LIST] Re: Query regarding XTK Files -
» [SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz -
» [SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz -
» [SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz -
» [SI-LIST] Re: Matched Length Constaint Approximation for abu s ru nning between 20-50MHz -
» [SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz -
» [SI-LIST] Re: simulation tool frequency setup -
» [SI-LIST] Clock-recovery for Dummies? -
» [SI-LIST] TDR and VNA web cast Tues August 20 -
» [SI-LIST] simulation tool frequency setup -
» [SI-LIST] How IBIS Simulator works? -
» [SI-LIST] Matched Length Constaint Approximation for a bus running between 20-50MHz -
» [SI-LIST] IBIS Model providers -
» [SI-LIST] East Coast SI / High Speed Design Engineer Available -
» [SI-LIST] Re: Lout of VRM -
» [SI-LIST] Re: DDR-II: timing analysis -
» [SI-LIST] Re: Lout of VRM -
» [SI-LIST] Re: Off-topic? Questions about measuring power supply ripple/noise (PARD) -
» [SI-LIST] Off-topic? Questions about measuring power supply ripple/noise (PARD) -
» [SI-LIST] Re: DDR-II: timing analysis -
» [SI-LIST] Re: Lout of VRM -
» [SI-LIST] Re: New appnote on PDS design -- XAPP623 -
» [SI-LIST] DDR-II: timing analysis -
» [SI-LIST] Re: AW: Re: DDR-II: SSTL_18 & ODT -
» [SI-LIST] Re: lost contact with engineer -
» [SI-LIST] PCB West and HDI Expo 2003 Final Call for Abstracts -
» [SI-LIST] Termination resistor drift -
» [SI-LIST] test - do not read -
» [SI-LIST] Re: Need help with hspice error -
» [SI-LIST] Re: Need help with hspice error -
» [SI-LIST] Re: Need help with hspice error -
» [SI-LIST] Need help with hspice error -
» [SI-LIST] Re: anti-resonance -
» [SI-LIST] Re: HSpice or HyperLynx -
» [SI-LIST] Lout of VRM -
» [SI-LIST] Re: Cost Factor of introducing Blind and BuriedVia s -
» [SI-LIST] Re: Bandwidth of Switching Requlators -
» [SI-LIST] Re: Using Planar Capacitors -
» [SI-LIST] ** www.hardware-guru.com ** -
» [SI-LIST] Ibis model for DVI Transmitter -
» [SI-LIST] AW: Re: DDR-II: SSTL_18 & ODT -
» [SI-LIST] Crosstalk Threshold for HSTL and SSTL I/Os -
» [SI-LIST] Re: Eye pattern generation in XTK -
» [SI-LIST] Re: Cost Factor of introducing Blind and Buried Vias -
» [SI-LIST] Re: DDR-II: SSTL_18 & ODT -
» [SI-LIST] Re: One decoupling cap per BGA power pin? -
» [SI-LIST] anti-resonance -
» [SI-LIST] Re: One decoupling cap per BGA power pin? -
» [SI-LIST] Re: One decoupling cap per BGA power pin? -
» [SI-LIST] Using Planar Capacitors -
» [SI-LIST] Eye pattern generation in XTK -
» [SI-LIST] Eye pattern generation in XTK -
» [SI-LIST] Re: Decoupling Capacitor -
» [SI-LIST] Re: Decoupling Capacitor -
» [SI-LIST] Cost Factor of introducing Blind and Buried Vias -
» [SI-LIST] Decoupling Capacitor -
» [SI-LIST] Bandwidth of Switching Requlators -
» [SI-LIST] How to merge noise waveform into passive signal waveform in XTK? -
» [SI-LIST] Re: HSpice or HyperLynx -
» [SI-LIST] Re: planer capacitors -
» [SI-LIST] Re: Query regarding XTK Files -
» [SI-LIST] Query regarding XTK Files -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] DC-DC converter -
» [SI-LIST] Re: SSO -
» [SI-LIST] Re: ISI -
» [SI-LIST] DDR-II: SSTL_18 & ODT -
» [SI-LIST] Re: SSO -
» [SI-LIST] Noise on Vcore -
» [SI-LIST] Re: New appnote on PDS design -- XAPP623 -
» [SI-LIST] Re: SSO -
» [SI-LIST] test message #2 -- ignore -
» [SI-LIST] test message #2 -- ignore -
» [SI-LIST] Re: ISI -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: Decoupling Capacitors -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Decoupling Capacitors -
» [SI-LIST] Re: HSpice or HyperLynx -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: ISI -
» [SI-LIST] Re: New appnote on PDS design -- XAPP623 -
» [SI-LIST] Re: HSpice or HyperLynx -
» [SI-LIST] Re: SSO -
» [SI-LIST] Re: ISI -
» [SI-LIST] Re: ISI -
» [SI-LIST] ISI -
» [SI-LIST] SSO -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: HSpice or HyperLynx -
» [SI-LIST] Re: ESD Structure in IBIS -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: si-list Digest V2 #219 -
» [SI-LIST] Re: ESD Structure in IBIS -
» [SI-LIST] Re: HSpice or HyperLynx -
» [SI-LIST] planer capacitors -
» [SI-LIST] Re: ESD Structure in IBIS -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: HSpice or HyperLynx -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeservedor not? -
» [SI-LIST] ESD Structure in IBIS -
» [SI-LIST] Re: HSpice or HyperLynx -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: LVDS vs RS422 -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: Eye pattern between QDR and FPGA -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] LVDS vs RS422 -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] HSpice or HyperLynx -
» [SI-LIST] How to modify IBIS model -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] New appnote on PDS design -- XAPP623 -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: Noise on BGA core voltage rail -
» [SI-LIST] Re: Eye pattern between QDR and FPGA -
» [SI-LIST] Re: MAX. IDE CABLE Length? -
» [SI-LIST] Noise on BGA core voltage rail -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Eye pattern between QDR and FPGA -
» [SI-LIST] Re: Ground plane split widths... -
» [SI-LIST] Re: MAX. IDE CABLE Length? -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? -
» [SI-LIST] Re: Ground plane split widths... -
» [SI-LIST] Re: Ground plane split widths... -
» [SI-LIST] Problems with a post: Re: ¦^«H¡G MAX. IDE CABLE Length? -
» [SI-LIST] Re: MAX. IDE CABLE Length? -
» [SI-LIST] ¦^«H¡G MAX. IDE CABLE Length? -
» [SI-LIST] ¦^«H¡G MAX. IDE CABLE Length? -
» [SI-LIST] ¦^«H¡G MAX. IDE CABLE Length? -
» [SI-LIST] MAX. IDE CABLE Length? -
» [SI-LIST] Re: Ground plane split widths... -
» [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? -
» [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: PCB tracks -
» [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] PCB tracks -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Ground plane split widths... -
» [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] Re: A question for the group -
» [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] Ground plane split widths... -
» [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] Re: Course on Signal Integrity at San Jose State Univ. -
» [SI-LIST] Re: active probe issues and effects on SI -
» [SI-LIST] active probe issues and effects on SI -
» [SI-LIST] Re: copper-to-copper separation -
» [SI-LIST] Re: copper-to-copper separation -
» [SI-LIST] Re: copper-to-copper separation -
» [SI-LIST] Re: Power supply filtering -
» [SI-LIST] Re: SSN Measurement -
» [SI-LIST] Re: copper-to-copper separation -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: copper-to-copper separation -
» [SI-LIST] Re: copper-to-copper separation -
» [SI-LIST] Re: copper-to-copper separation -
» [SI-LIST] copper-to-copper separation -
» [SI-LIST] Re: Placement of Decoupling Caps -
» [SI-LIST] Re: Output Capacitor of a switching Regulato -
» [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? -
» [SI-LIST] Antwort: Re: Placement of Decoupling Caps -
» [SI-LIST] Re: Series Termination -
» [SI-LIST] Re: Placement of Decoupling Caps -
» [SI-LIST] Re: Output Capacitor of a switching Regulato -
» [SI-LIST] Series Termination -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? -
» [SI-LIST] Re: Placement of Decoupling Caps -
» [SI-LIST] Re: Power supply filtering -
» [SI-LIST] Autorouting Algorithm? -
» [SI-LIST] Re: Placement of Decoupling Caps -
» [SI-LIST] Placement of Decoupling Caps -
» [SI-LIST] Re: Power supply filtering -
» [SI-LIST] -
» [SI-LIST] Re: Power supply filtering -
» [SI-LIST] Power supply filtering -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Ethernet switch burnout -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Blatant advertising -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Output Capacitor of a switching Regulator -
» [SI-LIST] Termination resistors -
» [SI-LIST] Ethernet switch burnout -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations - THINGS TO LOOK FOR -