[SI-LIST] IPC_2251 draft copy - bulk capacitance query
- From: Lum Wee Mei <lweemei@xxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 20 Aug 2002 08:51:46 +0800
Hello there,
With the recent interest in decoupling capacitor, I was going through the
IPC-2251(current IPC-D-317), 4th working draft and come across the following
sections that I hope someone can explain what it means :
5.1.4.3 Low Frequency (Bulk) Capacitance
Low frequency capacitance is often termed bulk capacitance. This capacitance
is used to recharge power planes and (Q1) higher frequency charging
capacitors and provide switching current for lower frequency requirments.
Generally, bulk capacitance is placed at each power input to the board. It
isalso distributed on the board in (Q2) an "area of influence" method to
supply the high frequency decoupling local charge current.
Q1 : if it is for low frequency how this low capacitance help to recharge
higher frequency capacitors?
Q2 : what is this "area of influence" method?
5.1.4.5 PWB Decoupling Recommendations
a) . . . . It is recommended that a 0.1uF capacitor be provided for unused
power supply connector pins.
Qn : Is there such case of unused power supply pins on connector or I have
mis-interpret the statement?
b) . . . . ECL/GTL signal line terminationr resistor packs and other devices
may require multiple high frequency decoupling capacitors. Generally 0.01uF
to 0.1uF ceramic SMT capacitors work best when placed directly beneath the
device on the back side of the board. As an alternate, capacitors may be
placed on the top side with short, wide closely spaced traces connected to
the IC pins via'd into the planes.
Qn : what is the obvious advantage of "placed directly beneath" and "on the
top with short, wide closely spaced traces"?
Qn : why closed spaced traces?
c) . . . Provide distributed bulk low frequency and mid frequency decoupling
capacitors near large programmable devices. Usually 2 to 4 capacitors each
4.7uF to 22uF tantalum capacitors (Q1) on 2 opposite corners works well. In
addition, 4.7 to 10uF capacitors should be distributed throughout the board
in (Q2) an "area of influence" or "predicted current flow area" method.
Q1 : why on 2 opposite corners?
Q2 : how to route this "area of influence" or "predicted current flow area"?
Hope to hear from you guys.
Thanks and warmest regards - Wee Mei
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