[SI-LIST] Re: DDR-II: timing analysis

I think that the 400MT/s (200MHz clock) is DDR-II.  There are Micron 
parts rated at that.  If not, the material should be directly applicable 
anyway.  
The same principles operate.  


----- Original Message ----- 
From: "Bret Stott" <bstott@xxxxxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, August 15, 2002 9:20 AM
Subject: [SI-LIST] Re: DDR-II: timing analysis


> 
> Hi John,
> 
> Thanks for pulling info out of the archives for me -- definitely helpful.
> However, the
> information is all about DDRI.  I'm looking for the same type of information
> (timing analysis, ref. designs) for DDR-II.
> 
> Thoughts?  Pointers?
> 
> Thanks,
> -Bret
> 
> 
> 
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of john lipsius
> Sent: Wednesday, August 14, 2002 9:20 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR-II: timing analysis
> 
> 
> 
> Bret,
> 
> See the si-list archives.
> > List archives are viewable at:
> > http://www.freelists.org/archives/si-list
> > or at our remote archives:
> > http://groups.yahoo.com/group/si-list/messages
> 
> 
> FROM A PRIOR THREAD...  see URLs in email body below
> subj:   DDR DRAM
> 
> The links to micron provide an example timing budget, which is
> what I assume you're looking for from the stds committee.
> 
> ----------------------------------------------------------------
> 
> ----- Original Message -----
> From: "john lipsius" <johnlipsius@xxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Sent: Thursday, May 09, 2002 1:13 AM
> Subject: [SI-LIST] Re: DDR DRAM
> 
> I agree with Kevin.  But it's hard to guarantee.  The following is only
> my 2 cents.
> 
> Also, sounds like 200MHz DDR, not something to attempt without a system
> timing budget.  The appearance is that a total timing budget isn't
> available.
> See links at the bottom.
> 
> That budget, with input from Spice results of  asic io, incl. clock chain
> delay
> and delay line logic, package, board traces & terminations, is
> required...Not to
> mention the noise budget.
> 
> If it's not available, then you're flying blind when you have to debug.
> If a board layout could fix this (sounds doubtful), it would require doing
> the Spice
> & timing budget, from which the answer would just "fall out", assuming the
> modeling
> is accurate.
> 
> ....Quick 'n Dirty....
> 
> > Placing parallel termination at ASIC end (680 ohms each to
> > 2.5V and Ground) seems to help the working of DRAM "X".
> 
> 1. Assuming the above is saying it helps but doesn't fix it, then this
> points to those
> 3 bits'
>     asic timing being problematic.  A pin-configurable delay line would
> help, if there
> is
>     such a thing.  Typically, the controller adaptively adjusts the delay on
> pwr up
> self test, I
>     believe.
> 
> 2. Lengthening DataStrobe trace might do the trick, but you have to watch
> out for the
>     effect on the write cycle.  Again, timing budget comin' atcha.
> 
> As Kevin said, any solution needs to be simulated at 4 corners.
> 
> Termination for Point-to-Point Systems
> http://www.micron.com/products/technote.jsp?path=/DRAM/DDR+SDRAM&fileID=584
> 
> DDR SDRAM timing budget....   it's a long read  ... good luck in your quest
> http://download.micron.com/pdf/pubs/designline/dl399.pdf
> http://download.micron.com/pdf/pubs/designline/DL92b.pdf
> 
> -John
> 
> 
> >
> > I think you need to show the timing analysis for sampling
> > read data.
> >
> > Micron has a very good app note that highlights different ways
> > of adding up the numbers.
> >
> > You mention that both DRAMs meet the jedec spec but your part
> > doesn't work.
> >
> > It sounds like you don't have the right delay line in your asic
> > to align the data and strobe appropriately, so that you can sample
> > correctly, given the jedec-spec'ed variances and variances in your
> > board layout.
> >
> > Before you can decide what you need to do to make your current
> > thing "better"...you need to figure out the full read timing analysis,
> > I think.
> >
> > For instance, if your design can tolerate extra read return latency,
> > it may be that you need to lengthen the data strobes on your board,
> > relative to the data.
> >
> > Without seeing the numbers, it's hard to say where you have margin
> > to play with. It's possible that your design doesn't have enough
> > skew tolerance inside the asic, so that you might not be able
> > to work for all corner cases, unless you make more drastic asic changes.
> >
> > I may be off base. Apologies if so.
> >
> > -kevin
> >
> > > Delivered-To: si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] Re: DDR DRAM
> > > To: si-list@xxxxxxxxxxxxx
> > > X-MIMETrack: Serialize by Router on D03NM028/03/M/IBM(Release 5.0.9a
> |January
> > 7, 2002) at 05/07/2002 09:26:52 AM
> > > MIME-Version: 1.0
> > > Content-Transfer-Encoding: 8bit
> > > X-archive-position: 2772
> > > X-ecartis-version: Ecartis v1.0.0
> > > X-original-sender: ajmani@xxxxxxxxxx
> > > X-list: si-list
> > >
> > >
> > >
> > > Hello SI-LISTers,
> > > Thanks to all of you who replied to my post.  A number of questions have
> > > been raised and I wish to answer them.
> > >
> > > 1) I used HP 2.5 GHz probes with HP Infinium 1.5 GHz oscilloscope, using
> 8
> > > GHz sampling rate.
> > >
> > > 2) I had gone through several Application Notes/other material and
> decided
> > > to use source terminations because of the following constraints:
> > >
> > >    a) I do not have enough board space to provide parallel terminations
> or
> > > both.
> > >
> > >    b) I am already exceeding our power budget, and can't afford the
> > > additional current drain of parallel terminations.
> > >
> > >    c) The parallel termination used by me (on the failing bits only)
> were
> > > selected by simulations and were also found to work on the actual card.
> > >
> > > The problem as I see is that brand "X" DRAM puts data after the Strobe
> > > (although still within their specs of 500 ps), whereas brand "Y" DRAM
> puts
> > > data before the Strobe.  Hence, I have a problem of matching my card
> layout
> > > to work with both DRAMs.
> > >
> > > Regards, Ravinder
> > > PCB Development and Design Department
> > > IBM Corporation
> > > Email: ajmani@xxxxxxxxxx
> 
> 
> 
> 
> ----- Original Message -----
> From: "Bret Stott" <bstott@xxxxxxxxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Sent: Wednesday, August 14, 2002 2:01 PM
> Subject: [SI-LIST] DDR-II: timing analysis
> 
> 
> >
> > Hi SI-gurus,
> >
> > Is anyone aware of a timing analysis for a DDR-II memory
> > system operating at 400, 533, and/or 667 MT/s that they can
> > share?  I'm assuming someoneon the standards committee must
> > have worked up some numbers to determine the DRAM timing specifications.
> >
> > Thanks,
> > -Bret
> >
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