[SI-LIST] Re: Clock-recovery for Dummies?

Manufacturers are a good starting point.

For some history, TI has an application note for a digital PLL in their 
document sdla005b.pdf (March 1997).

Philips has an implementation of the Alexander phase detector coupled with a 
ring oscillator (622 Mbits) 
http://www.semiconductors.philips.com/acrobat/datasheets/TZA3004HL_2.pdf

Some parts will work within a tight range of bit rates centred on standard 
comms frequencies (155 / 622 etc) over +-100pm.

Others, like the Cypress Hotlink parts function at any speed upto an upper 
limit (some parts 200 Mbits).

FPGAs from Altera include analog PLLs and CDR (an130.pdf).

Generally, FPGAs from Xilinx have digital PLLs (DLLs) and don't support the 
recovery of clock and data. However, there is a method of sampling the data at 
a slightly higher frequency than the bit rate that recovers data without 
recovering the clock (XAPP244), and there is a recent note XAPP250 (April 2002) 
that discusses CDR at upto 450 MHz in VirtexII parts in conjunction with an 
external VCO (for instance Maxim parts 2605 - 2609).

Regards

Jon Keeble






----- Original Message ----- 
From: "Steven Kan" <steven@xxxxxxxxxxxxxxxxxxxx>
To: "SI-List" <si-list@xxxxxxxxxxxxx>
Sent: Saturday, August 17, 2002 3:51 AM
Subject: [SI-LIST] Clock-recovery for Dummies?


> 
> Can someone recommend a good online introduction to practical applications
> of clock-recovery chips? We currently know nothing about these except for
> what goes in and what comes out :-)
> 
> Thanks!
> 
> 
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