[SI-LIST] Re: Noise on BGA core voltage rail
- From: "istvan novak" <istvan.novak@xxxxxxxxxxxxxxxx>
- To: <Anand.Kuriakose@xxxxxxxxxx>
- Date: Mon, 12 Aug 2002 22:41:43 -0400
Anand,
If you have power-ground planes with bypass capacitors on it, you have
the potential of creating two types of resonances (beyond the
(capacitor-to-capacitor antiresonances)
- capacitor-to-plane resonance (this was your question)
- modal plane resonances
The above resonance modes are linked together by the way how
you can fight them. A simple way to reduce both of them by using
the smallest number of parts, you have to
- determine the equivalent characteristic impedance of the planes
- make sure that the equivalent cumulative resistance of bypass capacitors
matches the plane equivalent impedance (this will reduce the
modal plane resonances)
- AND make sure that the equivalent inductance of bypass capacitors
is much less than the equivalent inductance of your planes (these two
conditions will greatly reduce the capacitor-plane resonance)
Note: as it was mentioned earlier on this list, these potential resonances
do
not cause any problem to you if you make sure that either you dont excite
the resonances, or if you excite them the resulting noise is still OK for
your system.
regards
Istvan Novak
SUN Microsystems
----- Original Message -----
From: "ANAND KURIAKOSE" <Anand.Kuriakose@xxxxxxxxxx>
To: <Larry.Smith@xxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>; <ikhan@xxxxxxxxxxxxxxxxxxx>
Sent: Friday, August 09, 2002 1:47 PM
Subject: [SI-LIST] Re: Noise on BGA core voltage rail
>
> Larry,
>
> How to counter the effect of parallel resonance occuring due to the
> equivalent inductance offered by the decaps and the power plane
capacitance?
>
> Anand.
>
>
>
>
> From: Larry Smith <Larry.Smith@xxxxxxx> on 08/09/2002 02:36 AM
> Please respond to Larry.Smith@xxxxxxx@SMTP@Exchange
> To: si-list@xxxxxxxxxxxxx@SMTP@Exchange,
> ikhan@xxxxxxxxxxxxxxxxxxx@SMTP@Exchange
> cc:
>
> Subject: [SI-LIST] Re: Noise on BGA core voltage rail
>
>
> Ibrahim - The plane impedance is calculated from the capacitance per
> area and the inductance per square. For many SI structures,
> impedance
> is the square root of inductance divided by capacitance, Z =
> sqrt(L/C).
>
> Capacitance of power planes is easily calculated from the dielectric
> constant (dK) and thickness. Capacitance per unit area is dK/thk.
> 1
> mil of FR4 (dK=4) has about 900pF per square inch, 2 mil thick FR4
> has
> about 450 pF/in^2, etc.
>
> One way to calculate inductance is from velocity. Velocity in FR4
> is
> the speed of light divided by sqrt(dK), vel=C_light/sqrt(dK).
> Velocity
> may also be calculated from sqrt(LC) from electromagnetic or
> transmission line theory. From these concepts, L_a = 1/(C_a*vel^2) ,
> where L_a is the power plane spreading inductance, C_a is the
> capacitance per unit area and vel is the velocity of electromagnetic
> propagation in the FR4 dielectric, about 6 inches per nSec. The
> inductance of power planes separated by 1 mil of FR4 is about 30
> pH/square, 2 mils is twice that, etc.
>
> The power plane impedance is then easily calculated from inductance
> and
> capacitance by the formula in the first paragraph. A pair of power
> planes with 1 mil FR4 between conductors has 185 mOhm-inch. A 1
> inch
> wide strip has 185 mOhms, 2 inch wide is half of that. Double the
> dielectric thickness and you double the impedance, similar to
> transmission lines.
>
> These concepts are discussed in much more detail in a paper located
> in:
>
> http://groups.yahoo.com/group/si-list/files/
>
> Follow the trail to papers from Sun Microsystems and look at
> cpmt_2001.pdf "Power Plane SPICE Models and Simulated Performance
> for
> Materials and Geometries". This paper discusses power plane
> impedance
> and spreading inductance in much more detail. These are the
> properties
> to be concerned about when trying to build a low impedance power
> distribution system.
>
> 2nd question, yes. If you have multiple power plane rails, you have
> to have a ground plane adjacent to each one of them to establish
> a low impedance power rail.
>
> regards,
> Larry Smith
> Sun Microsystems
>
>
> > From: "Ibrahim Khan" <ikhan@xxxxxxxxxxxxxxxxxxx>
> > To: <si-list@xxxxxxxxxxxxx>
> >
> >
> > This is great place to learn.
> >
> > Larry,
> > 1. How do we calculate the plane impedance?
> > 2. If you have multiple power rails, do you have to have ground
> plane
> > next to every power plane for the decaps of that rail to
> effective?
> >
> > Regards
> > Ibrahim Khan
> > -----Original Message-----
> > From: Larry Smith [mailto:Larry.Smith@xxxxxxx]=20
> > Sent: Thursday, August 08, 2002 12:33 PM
> > To: si-list@xxxxxxxxxxxxx; Anand.Kuriakose@xxxxxxxxxx
> > Subject: [SI-LIST] Re: Noise on BGA core voltage rail
> >
> >
> >
> > Anand - It is difficult to do anything about power distribution
> noise at
> > 200 MHz and above by using discreet decoupling capacitors.
> >
> > Your best ally at high frequency is the PCB power planes. They
> are
> > effective at high frequency but may have cavity resonances which
> depend
> > upon the dimensions of the board.
> >
> > The best way to make the PCB power planes effective is by defining
> a
> > stackup that has power/Gnd plane pairs next to each other. The
> > dielectric thickness between the planes determines the capacitance
> and
> > spreading inductance of the planes. Thinner is better. 4 mils
> between
> > planes is good, 2 mils is better.
> >
> > Several years ago, it was common to see power and ground planes
> > separated by 14 mils or so in order to accommodate 2 signal layers
> > between the planes. With that spacing, the performance of the
> > decoupling capacitors is limited by the spreading inductance of
> the
> > power planes. If you have more than a few dozen ceramic
> capacitors, you
> > must use adjacent power planes in the stackup in order to make
> them
> > effective. Otherwise, the impedance of the planes dominates over
> the
> > impedance of the capacitors at high frequency.
> >
> > regards,
> > Larry Smith
> > Sun Microsystems
> >
> > > Delivered-To: si-list@xxxxxxxxxxxxx
> > > X-Lotus-FromDomain: APEX DATA INC
> > > From: Anand.Kuriakose@xxxxxxxxxx
> > > To: si-list@xxxxxxxxxxxxx
> > > Date: Thu, 8 Aug 2002 22:06:59 +0630
> > > Subject: [SI-LIST] Noise on BGA core voltage rail
> > > Mime-Version: 1.0
> > > Content-Disposition: inline
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> > > X-archive-position: 3678
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> > > X-list: si-list
> > >=20
> > >=20
> > >=20
> > >=20
> > > Hi,
> > >=20
> > > Heres a situation where i have a BGA (chipset with interface
> to=20
> > > processor, DDR memory and other high speed proprietry buses)
> with=20
> > > sufficient decoupling sprinkled around the BGA. The decoupling
> on the=20
> > > core voltage rail (2.5V, which is also the I/O voltage for
> DDR=20
> > > interface) basically consists of 2 high value bulk capacitors,
> six=20
> > > 1uf caps, ten each of 0.1uF and 0.01uF caps. I am
> > noticing
> > > noise around 150mv of noise during activity on the DDR (using
> software
> > > utilities) and roughly 80-100 mV during almost no activity
> across the
> >
> > > chip. This amplitude is significantly more than the noise
> noticed at=20
> > > other high
> > speed
> > > chips on the board. Using the FFT function on the DSO, i figured
> out=20
> > > that the frequencies where it peaks are 200Mhz and integral
> multiples=20
> > > of 200Mhz.
> > >=20
> > > I tried a couple of things:
> > >=20
> > > 1> Since i am seeing peaks at 200Mhz and its integral
> multiples, i=20
> > > 1> thought
> > > that there could be insufficient high frequency decoupling and
> hence i
> >
> > > replace the 0.1uF caps with 1000pF caps.
> > > 2> Secondly, fearing that there could be some resonance
> happening=20
> > > 2> due the
> > > different values of caps used, i replaced all the 0.1 uF caps
> with=20
> > > 0.01uF caps (in addition to existing 0.01uF caps).
> > >=20
> > > Both the above strategies failed to reduce the noise. There was
> no=20
> > > change in
> > the
> > > amplitude of the noise and also the frequencies where peaks
> were=20
> > > noticed.
> > >=20
> > > Can somebody out there throw some light on what is lacking in
> the=20
> > > strategies mentioned above and how to reduce this noise=20
> > > satisfactorily.
> > >=20
> > > Thanx in advance.
> > > Anand.
> > >=20
> > >=20
>
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