[SI-LIST] Re: Noise on BGA core voltage rail
- From: Larry Smith <Larry.Smith@xxxxxxx>
- To: Anand.Kuriakose@xxxxxxxxxx
- Date: Thu, 8 Aug 2002 13:26:16 -0700 (PDT)
Anand - Two power/Gnd pairs with 4 mil separation should be sufficient
for your application, at least to the degree that I understand it.
Be very careful about the mounting inductance for your capacitors. All
the capacitors in parallel become an equivalent inductance at
frequencies above the series resonance of the lowest value capacitor.
This equivalent inductance is in parallel with the power plane
capacitance, forming an LC tank circuit. It has a high impedance
resonance at some frequency, quite possibly at your 200 MHz problem
frequency.
The other thing that you have to watch out for is cavity resonances of
the power planes. You can easily get impedance peaks in the 100 to 600
MHz range. If impedance peaks are stimulated by the clock, its harmonics,
I/O communication or core code patterns, you will see a lot of noise
on the power distribution system at the peak frequencies.
BTW, it is possible to put enough high frequency capacitors in parallel
to be effective at hundreds of MHz, but it takes a lot of them. They
will not be effective if you have high impedance power planes. Work
with the power planes first..
regards,
Larry Smith
Sun Microsystems
> From: ANAND KURIAKOSE <Anand.Kuriakose@xxxxxxxxxx>
> To: Larry Smith <Larry.Smith@xxxxxxx>
> Cc: si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Noise on BGA core voltage rail
> Date: Thu, 8 Aug 2002 10:07:33 -0700
> MIME-Version: 1.0
>
> Hi Larry,
>
> The board has 2 power-ground pairs. The spacing b/n the power and
> the ground plane is 4 mils. The power planes carry 2.5 V rail (the noisy
> rail) along with other volttages on the board.
>
> I have one question.
>
> In addition to having power-ground pairs yeilding low impedances at
> high frequencies above 100Mhz (which seems to be the only solution according
> to you), what other precautions should be taken during the design or layout
> to have low target impedances from DC to around 200Mhz-600Mhz?
>
> Anand.
>
>
>
>
> From: Larry Smith <Larry.Smith@xxxxxxx> on 08/09/2002 12:03 AM
> Please respond to Larry Smith <Larry.Smith@xxxxxxx>@SMTP@Exchange
> To: si-list@xxxxxxxxxxxxx@SMTP@Exchange, ANAND KURIAKOSE/Apex
> Data Inc/01@Apex Data Inc
> cc:
>
> Subject: Re: [SI-LIST] Noise on BGA core voltage rail
>
> Anand - It is difficult to do anything about power distribution
> noise
> at 200 MHz and above by using discreet decoupling capacitors.
>
> Your best ally at high frequency is the PCB power planes. They are
> effective at high frequency but may have cavity resonances which
> depend
> upon the dimensions of the board.
>
> The best way to make the PCB power planes effective is by defining a
> stackup that has power/Gnd plane pairs next to each other. The
> dielectric thickness between the planes determines the capacitance
> and
> spreading inductance of the planes. Thinner is better. 4 mils
> between
> planes is good, 2 mils is better.
>
> Several years ago, it was common to see power and ground planes
> separated by 14 mils or so in order to accommodate 2 signal layers
> between the planes. With that spacing, the performance of the
> decoupling capacitors is limited by the spreading inductance of the
> power planes. If you have more than a few dozen ceramic capacitors,
> you must use adjacent power planes in the stackup in order to make
> them
> effective. Otherwise, the impedance of the planes dominates over
> the
> impedance of the capacitors at high frequency.
>
> regards,
> Larry Smith
> Sun Microsystems
>
> > Delivered-To: si-list@xxxxxxxxxxxxx
> > X-Lotus-FromDomain: APEX DATA INC
> > From: Anand.Kuriakose@xxxxxxxxxx
> > To: si-list@xxxxxxxxxxxxx
> > Date: Thu, 8 Aug 2002 22:06:59 +0630
> > Subject: [SI-LIST] Noise on BGA core voltage rail
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> >
> >
> >
> >
> > Hi,
> >
> > Heres a situation where i have a BGA (chipset with interface to
> processor, DDR
> > memory and other high speed proprietry buses) with sufficient
> decoupling
> > sprinkled around the BGA. The decoupling on the core voltage rail
> (2.5V, which
> > is also the I/O voltage for DDR interface) basically consists of
> 2 high value
> > bulk capacitors, six 1uf caps, ten each of 0.1uF and 0.01uF caps.
> I am
> noticing
> > noise around 150mv of noise during activity on the DDR (using
> software
> > utilities) and roughly 80-100 mV during almost no activity across
> the chip.
> > This amplitude is significantly more than the noise noticed at
> other high
> speed
> > chips on the board. Using the FFT function on the DSO, i figured
> out that the
> > frequencies where it peaks are 200Mhz and integral multiples of
> 200Mhz.
> >
> > I tried a couple of things:
> >
> > 1> Since i am seeing peaks at 200Mhz and its integral multiples,
> i thought
> > that there could be insufficient high frequency decoupling and
> hence i replace
> > the 0.1uF caps with 1000pF caps.
> > 2> Secondly, fearing that there could be some resonance
> happening due the
> > different values of caps used, i replaced all the 0.1 uF caps with
> 0.01uF caps
> > (in addition to existing 0.01uF caps).
> >
> > Both the above strategies failed to reduce the noise. There was no
> change in
> the
> > amplitude of the noise and also the frequencies where peaks were
> noticed.
> >
> > Can somebody out there throw some light on what is lacking in the
> strategies
> > mentioned above and how to reduce this noise satisfactorily.
> >
> > Thanx in advance.
> > Anand.
> >
> >
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>
>
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