[SI-LIST] Re: Noise on BGA core voltage rail
- From: "Ibrahim Khan" <ikhan@xxxxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 8 Aug 2002 12:52:07 -0500
This is great place to learn.
Larry,
1. How do we calculate the plane impedance?
2. If you have multiple power rails, do you have to have ground plane
next to every power plane for the decaps of that rail to effective?
Regards
Ibrahim Khan
-----Original Message-----
From: Larry Smith [mailto:Larry.Smith@xxxxxxx]=20
Sent: Thursday, August 08, 2002 12:33 PM
To: si-list@xxxxxxxxxxxxx; Anand.Kuriakose@xxxxxxxxxx
Subject: [SI-LIST] Re: Noise on BGA core voltage rail
Anand - It is difficult to do anything about power distribution noise at
200 MHz and above by using discreet decoupling capacitors.
Your best ally at high frequency is the PCB power planes. They are
effective at high frequency but may have cavity resonances which depend
upon the dimensions of the board.
The best way to make the PCB power planes effective is by defining a
stackup that has power/Gnd plane pairs next to each other. The
dielectric thickness between the planes determines the capacitance and
spreading inductance of the planes. Thinner is better. 4 mils between
planes is good, 2 mils is better.
Several years ago, it was common to see power and ground planes
separated by 14 mils or so in order to accommodate 2 signal layers
between the planes. With that spacing, the performance of the
decoupling capacitors is limited by the spreading inductance of the
power planes. If you have more than a few dozen ceramic capacitors, you
must use adjacent power planes in the stackup in order to make them
effective. Otherwise, the impedance of the planes dominates over the
impedance of the capacitors at high frequency.
regards,
Larry Smith
Sun Microsystems
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> Date: Thu, 8 Aug 2002 22:06:59 +0630
> Subject: [SI-LIST] Noise on BGA core voltage rail
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>=20
>=20
>=20
>=20
> Hi,
>=20
> Heres a situation where i have a BGA (chipset with interface to=20
> processor, DDR memory and other high speed proprietry buses) with=20
> sufficient decoupling sprinkled around the BGA. The decoupling on the=20
> core voltage rail (2.5V, which is also the I/O voltage for DDR=20
> interface) basically consists of 2 high value bulk capacitors, six=20
> 1uf caps, ten each of 0.1uF and 0.01uF caps. I am
noticing
> noise around 150mv of noise during activity on the DDR (using software
> utilities) and roughly 80-100 mV during almost no activity across the
> chip. This amplitude is significantly more than the noise noticed at=20
> other high
speed
> chips on the board. Using the FFT function on the DSO, i figured out=20
> that the frequencies where it peaks are 200Mhz and integral multiples=20
> of 200Mhz.
>=20
> I tried a couple of things:
>=20
> 1> Since i am seeing peaks at 200Mhz and its integral multiples, i=20
> 1> thought
> that there could be insufficient high frequency decoupling and hence i
> replace the 0.1uF caps with 1000pF caps.
> 2> Secondly, fearing that there could be some resonance happening=20
> 2> due the
> different values of caps used, i replaced all the 0.1 uF caps with=20
> 0.01uF caps (in addition to existing 0.01uF caps).
>=20
> Both the above strategies failed to reduce the noise. There was no=20
> change in
the
> amplitude of the noise and also the frequencies where peaks were=20
> noticed.
>=20
> Can somebody out there throw some light on what is lacking in the=20
> strategies mentioned above and how to reduce this noise=20
> satisfactorily.
>=20
> Thanx in advance.
> Anand.
>=20
>=20
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