Posts for si-list, 09-2002

Browse: Last Month: 08-2002 Main Archive Page Next Month: 10-2002

» [SI-LIST] 2.5Gbit connectors and cables -
» [SI-LIST] Multiple drivers and receivers on one net. -
» [SI-LIST] Re: Can I get this from an IBIS model? -
» [SI-LIST] IBIS ramp problem in Hspice -
» [SI-LIST] GTLP VOH documentation -
» [SI-LIST] W-elements -
» [SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM -
» [SI-LIST] Re: Can I get this from an IBIS model? -
» [SI-LIST] Re: Can I get this from an IBIS model? -
» [SI-LIST] A SPICE TO IBIS CONVERSION PROBLEM -
» [SI-LIST] Re: Can I get this from an IBIS model? -
» [SI-LIST] Re: Differential pair impedance -
» [SI-LIST] Re: Can I get this from an IBIS model? -
» [SI-LIST] Can I get this from an IBIS model? -
» [SI-LIST] SI Class in Boston -
» [SI-LIST] Re: Differential pair impedance -
» [SI-LIST] USB 1.1 Cable Model -
» [SI-LIST] Re: Differential pair impedance -
» [SI-LIST] Re: Differential pair impedance -
» [SI-LIST] Re: Differential pair impedance -
» [SI-LIST] Re: Differential pair impedance -
» [SI-LIST] Re: Differential pair impedance -
» [SI-LIST] Differential pair impedance -
» [SI-LIST] Re: Buried capacitance materials -
» [SI-LIST] Re: slew rate and driver impedance -
» [SI-LIST] Re: slew rate and driver impedance -
» [SI-LIST] Re: slew rate and driver impedance -
» [SI-LIST] FW: intel-situg: Driver Model for TEK TDR heads? -
» [SI-LIST] slew rate and driver impedance -
» [SI-LIST] Re: Buried capacitance materials -
» [SI-LIST] Re: Buried capacitance materials -
» [SI-LIST] fwd: SI Tools -
» [SI-LIST] Re: Buried capacitance materials -
» [SI-LIST] Simulate a microprocessor in PSpice through a C program or with Matlab? -
» [SI-LIST] Re: Simulation problems with SSTL2 IBIS model (TI CDCV8 50) -
» [SI-LIST] Presentation slides available for download -
» [SI-LIST] Re: Capacitance calculator -
» [SI-LIST] Looking for SI position -
» [SI-LIST] Re: Capacitance calculator -
» [SI-LIST] Capacitance calculator -
» [SI-LIST] Re: IBIS model problems -
» [SI-LIST] AW: Simulation problems with SSTL2 IBIS model (TI CDCV850) -
» [SI-LIST] Re: SI Tools -
» [SI-LIST] Re: SI Tools -
» [SI-LIST] Re: current probe calibration -
» [SI-LIST] IBIS model problems -
» [SI-LIST] Re: GTL buffers Vref -
» [SI-LIST] Re: GTL buffers Vref -
» [SI-LIST] Re: Simulation problems with SSTL2 IBIS model -
» [SI-LIST] Re: Ethernet tools -
» [SI-LIST] Re: Simulation problems with SSTL2 IBIS model -
» [SI-LIST] Ethernet tools -
» [SI-LIST] Simulation problems with SSTL2 IBIS model -
» [SI-LIST] Re: Buried capacitance materials -
» [SI-LIST] current probe calibration -
» [SI-LIST] Buried capacitance materials -
» [SI-LIST] max current value on a pcb trace -
» [SI-LIST] Re: high speed circuit diagram? -
» [SI-LIST] LAN EMI/SI question -
» [SI-LIST] Re: high speed circuit diagram? -
» [SI-LIST] high speed circuit diagram? -
» [SI-LIST] HP 5372A -
» [SI-LIST] Re: max current value on a PCB trace -
» [SI-LIST] Re: max current value on a PCB trace -
» [SI-LIST] max current value on a PCB trace -
» [SI-LIST] Re: Signal Integrity Engineer Opportunity in theHeart of the Ozarks -
» [SI-LIST] Spectrum analyzer problem, noise -
» [SI-LIST] Re: Slide Rules. -
» [SI-LIST] Post- route analysis error -
» (no subject) -
» [SI-LIST] Re: Ansoft HFSS - inductive xtalk setup 2 -
» [SI-LIST] Ansoft HFSS - inductive xtalk setup 2 -
» [SI-LIST] Re: Ansoft HFSS - inductive xtalk setup -
» [SI-LIST] SI Tools -
» [SI-LIST] Ansoft HFSS - inductive xtalk setup -
» [SI-LIST] Re: Simple tool for FIR filters -
» [SI-LIST] EMC2003 in Turkey -
» [SI-LIST] Re: AC/DC impedance spec for floppy and 40Pin-IDEcable s. -
» [SI-LIST] Re: Trace resistance inductance -
» [SI-LIST] Re: Trace resistance inductance -
» [SI-LIST] Re: Trace resistance inductance -
» [SI-LIST] Re: We ought to address mutual SI-EMI issues in this forum -
» [SI-LIST] AW: Re: Rj-45 connectors isolation properties -
» [SI-LIST] AW: Re: Rj-45 connectors isolation properties -
» [SI-LIST] Package ball inductance -
» [SI-LIST] Reminder: Sep Meeting of RMCEMC -
» [SI-LIST] Re: Parasitic capacitance of vias -
» [SI-LIST] Re: Parasitic capacitance of vias -
» [SI-LIST] Re: AC/DC impedance spec for floppy and 40Pin-IDE cables. -
» [SI-LIST] Re: AC/DC impedance spec for floppy and 40Pin-IDE cables. -
» [SI-LIST] AC/DC impedance spec for floppy and 40Pin-IDE cables. -
» [SI-LIST] Trace resistance inductance -
» [SI-LIST] Simple tool for FIR filters -
» [SI-LIST] Re: Slide Rules. (Was Re: We ought to address mutua l SI-EMI issues in this forum) -
» [SI-LIST] Re: Slide Rules. (Was Re: We ought to address mutua l SI-EMI issues in this forum) -
» [SI-LIST] Re: Slide Rules. -
» [SI-LIST] Re: Slide Rules. (Was Re: We ought to address mutual SI-EMI issues in this forum) -
» [SI-LIST] Re: Slide Rules. (Was Re: We ought to address mutual SI-EMI issues in this forum) -
» [SI-LIST] Re: We ought to address mutual SI-EMI issues inthi s forum -
» [SI-LIST] Re: Question: Obtaining I/V and Switiching Info via lab measurments -
» [SI-LIST] Re: We ought to address mutual SI-EMI issues in thi s forum -
» [SI-LIST] Re: We ought to address mutual SI-EMI issues in thi s forum -
» [SI-LIST] Re: We ought to address mutual SI-EMI issues inthi s forum -
» [SI-LIST] Re: Slide Rules. (Was Re: We ought to address mutual SI-EMI issues in this forum) -
» [SI-LIST] si-list digest TOC strangeness -
» [SI-LIST] Slide Rules. (Was Re: We ought to address mutual SI-EMI issues in this forum) -
» [SI-LIST] Re: Parasitic capacitance of vias -
» [SI-LIST] Re: We ought to address mutual SI-EMI issues in this forum -
» [SI-LIST] Re: Parasitic capacitance of vias -
» [SI-LIST] Re: A simple problem about setup time -
» [SI-LIST] A simple problem about setup time -
» [SI-LIST] Re: Ethernet switch problems: detailed questions -
» [SI-LIST] Re: Parasitic capacitance of vias -
» [SI-LIST] Parasitic capacitance of vias -
» [SI-LIST] Re: Ethernet switch problems: detailed questions -
» [SI-LIST] Re: We ought to address mutual SI-EMI issues in this forum -
» [SI-LIST] Re: Ethernet switch problems: detailed questions -
» [SI-LIST] Ethernet switch problems: detailed questions -
» [SI-LIST] Re: FW: We ought to address mutual SI-EMI issues in this forum -
» [SI-LIST] Re: FW: We ought to address mutual SI-EMI issues in this forum -
» [SI-LIST] Re: Termination resistance value for GTL+ bus -
» [SI-LIST] Re: FW: We ought to address mutual SI-EMI issues in this forum -
» [SI-LIST] Re: Termination resistance value for GTL+ bus -
» [SI-LIST] Re: Clocks and translators -
» [SI-LIST] SI Job description of our ideal candidate -
» [SI-LIST] Re: ECL Terminations -
» [SI-LIST] Re: Termination resistance value for GTL+ bus -
» [SI-LIST] Clocks and translators -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Calculating power plane capacitance -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] 10ma Current Loop differntial impedance -
» [SI-LIST] Re: ECL terminations -
» [SI-LIST] Re: Signal Integrity Books -
» [SI-LIST] Signal Integrity Books -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] ECL terminations -
» [SI-LIST] Termination resistance value for GTL+ bus -
» [SI-LIST] Re: High Temp Mil Standard Oscillators -
» [SI-LIST] Re: High Temp Mil Standard Oscillators -
» [SI-LIST] High Temp Mil Standard Oscillators -
» [SI-LIST] Re: Rj-45 connectors isolation properties -
» [SI-LIST] Sigrity Offers Free Training of SI Tools -
» [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination -
» [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: SFF to SFP adapter board -
» [SI-LIST] Re: SONET Sync card -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Serpentine Traces -
» [SI-LIST] Re: Hspice class -
» [SI-LIST] Hspice class -
» [SI-LIST] Re: pspice -
» [SI-LIST] Re: about 'flat region' -
» [SI-LIST] pspice pwm ic model -
» [SI-LIST] ARCHIVED: SI Measurement Seminar -
» [SI-LIST] Re: PSPICE -
» [SI-LIST] Re: Startup time of SAW Resonators -
» [SI-LIST] Choose the correct ground symbol -
» [SI-LIST] Re: PSPICE -
» [SI-LIST] Re: PSPICE -
» [SI-LIST] Re: PSPICE -
» [SI-LIST] Re: PSPICE -
» [SI-LIST] PSPICE -
» [SI-LIST] Re: Startup time of SAW Resonators -
» [SI-LIST] Kirchoff and Faraday voltage measurements and simulations -
» [SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz -
» [SI-LIST] Ground Fill Question -
» [SI-LIST] HELP£¡ -
» [SI-LIST] Where can I get AGP8X ibis and ebd file? -
» [SI-LIST] PC200/PC266 184 Pin DDR Registered DIMM Ref Design -
» [SI-LIST] Re: Need picture or drawing of uneven coating -
» [SI-LIST] Re: Complex number -
» [SI-LIST] Re: about 'flat region' -
» [SI-LIST] Re: Complex number -
» [SI-LIST] Recommendation on a good intermediate to advanced SI class/course? -
» [SI-LIST] Re: about 'flat region' -
» [SI-LIST] Complex number -
» [SI-LIST] Need picture or drawing of uneven coating -
» [SI-LIST] about 'flat region' -
» [SI-LIST] using 4195A network/spectrum analyzer.... -
» [SI-LIST] Re: IBIS modeling services providers -
» [SI-LIST] Re: coaxial cable? -
» [SI-LIST] Re: coaxial cable? -
» [SI-LIST] Startup time of SAW Resonators -
» [SI-LIST] AW: Rj-45 connectors isolation properties -
» [SI-LIST] AW: Rj-45 connectors isolation properties -
» [SI-LIST] AW: Rj-45 connectors isolation properties -
» [SI-LIST] edge slope in eye diagram -
» [SI-LIST] Re: IBIS modeling services providers -
» [SI-LIST] Rj-45 connectors isolation properties -
» [SI-LIST] Antw: IBIS modeling services providers -
» [SI-LIST] IBIS modeling services providers -
» [SI-LIST] 3.125Gbps trace routing -
» [SI-LIST] Re: We ought to address mutual SI-EMI issues in this forum -
» [SI-LIST] Questions about Power Distribution -
» [SI-LIST] Re: General Trace Impedance -
» [SI-LIST] Re: General Trace Impedance -