Posts for si-list, 07-2002

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» [SI-LIST] Re: Output Capacitor of a switching Regulator -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Re: Layout service recommendations -
» [SI-LIST] Layout service recommendations -
» [SI-LIST] Re: OODB++ query -
» [SI-LIST] OODB++ query -
» [SI-LIST] GPPO Edge Launch -- Experiences > 10 GHz / Proper Mount? -
» [SI-LIST] Re: Output Capacitor of a switching Regulator -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeservedor not? -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Issues with Midpoint Crossing of DifferentialIBIS Buffer -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deservedor not? -
» [SI-LIST] Re: Issues with Midpoint Crossing of Differential IBIS Buffer -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Issues with Midpoint Crossing of Differential IBIS Buffer -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? -
» [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? -
» [SI-LIST] Roger O Wittman/GDIS/GDYN is out of the office. -
» [SI-LIST] Re: measuring i/o power without disrupting signalquality -
» [SI-LIST] Re: measuring i/o power without disrupting signalquality -
» [SI-LIST] Course on Signal Integrity at San Jose State Univ. -
» [SI-LIST] Output Capacitor of a switching Regulator -
» [SI-LIST] -
» [SI-LIST] Re: measuring i/o power without disrupting signalquality -
» [SI-LIST] Re: Modeling Simultaneous Switching Noise -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or... -
» [SI-LIST] Re: help ?why my eye is like this ?? -
» [SI-LIST] Re: Routing over a plane split -
» [SI-LIST] help ?why my eye is like this ?? -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Modeling Simultaneous Switching Noise -
» [SI-LIST] Routing over a plane split -
» [SI-LIST] measuring i/o power without disrupting signal quality -
» [SI-LIST] Re: Slot Antenna -
» [SI-LIST] Re: A question for the group -
» [SI-LIST] Re: PCI daughter card signal trace length -
» [SI-LIST] Re: Slot Antenna -
» [SI-LIST] Best board design for edge launch SMA to differential -
» [SI-LIST] Re: PCI daughter card signal trace length -
» [SI-LIST] IBIS Version 4.0 is released -
» [SI-LIST] job opening at GigaTest Labs -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Determining timing budgets using IBIS -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Determining timing budgets using IBIS -
» [SI-LIST] Re: A question for the group -
» [SI-LIST] Re: PCI daughter card signal trace length -
» [SI-LIST] voltage mode and current mode logic -
» [SI-LIST] PCI daughter card signal trace length -
» [SI-LIST] Re: Determining timing budgets using IBIS -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: i love this place !!! -
» [SI-LIST] Re: Slot Antenna -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Reflection Simulation -
» [SI-LIST] Determining timing budgets using IBIS -
» [SI-LIST] Re: ibis limitations -
» [SI-LIST] Re: ibis limitations -
» [SI-LIST] Re: Slot Antenna -
» [SI-LIST] Re: ibis limitations -
» [SI-LIST] HSPICE W-element transmission line model accuracy? -
» [SI-LIST] Re: ibis limitations -
» [SI-LIST] ibis limitations -
» [SI-LIST] Re: A question for the group -
» [SI-LIST] Re: A question for the group -
» [SI-LIST] Re: A question for the group -
» [SI-LIST] A question for the group -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] -
» [SI-LIST] -
» [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? -
» [SI-LIST] Re: LVDS RECEIVER IBIS MODEL -
» [SI-LIST] Re: Package in IBIS Bench Files -
» [SI-LIST] Package in IBIS Bench Files -
» [SI-LIST] hello -
» [SI-LIST] i love this place !!! -
» [SI-LIST] who have this paper -
» [SI-LIST] remove -
» [SI-LIST] Re: LVDS RECEIVER IBIS MODEL -
» [SI-LIST] Re: Message submitted to 'si-list' -
» [SI-LIST] Re: Job Openings at Sigrity -
» [SI-LIST] Job Openings at Sigrity -
» [SI-LIST] Re: HSPICE error -
» [SI-LIST] Re: HSPICE error -
» [SI-LIST] Re: HSPICE error -
» [SI-LIST] Re: Message submitted to 'si-list' -
» [SI-LIST] Re: LVDS RECEIVER IBIS MODEL -
» [SI-LIST] LVDS RECEIVER IBIS MODEL -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] Re: doubt about crosstalk -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] dont understand -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] dont understand -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] How should we terminate unused HSTL Outputs. -
» [SI-LIST] Recall: -
» [SI-LIST] Crosstalk -
» [SI-LIST] -
» [SI-LIST] Re: HSTL Terminations -
» [SI-LIST] Re: doubt about crosstalk. -
» [SI-LIST] doubt about crosstalk. -
» [SI-LIST] doubt about crosstalk. -
» [SI-LIST] HSTL Terminations -
» [SI-LIST] Re: Archived broadcast -
» [SI-LIST] Archived broadcast -
» [SI-LIST] Re: Pre-emphasis and IBIS -
» [SI-LIST] Re: Pre-emphasis and IBIS -
» [SI-LIST] Re: Pre-emphasis and IBIS -
» [SI-LIST] Re: ** www.hardware-guru.com ** -
» [SI-LIST] Re: ** www.hardware-guru.com ** -
» [SI-LIST] Re: ** www.hardware-guru.com ** -
» [SI-LIST] ** www.hardware-guru.com ** -
» [SI-LIST] ** www.hardware-guru.com ** -
» [SI-LIST] Re: how to evaluate the maximum overhsoot/undershoot -
» [SI-LIST] Re: package model -
» [SI-LIST] package model -
» [SI-LIST] Re: how to evaluate the maximum overhsoot/undershoot -
» [SI-LIST] how to evaluate the maximum overhsoot/undershoot -
» [SI-LIST] return loop current distribution -
» [SI-LIST] Re: Pre-emphasis and IBIS -
» [SI-LIST] Re: Pre-emphasis and IBIS -
» [SI-LIST] Re: Pre-emphasis and IBIS -
» [SI-LIST] Power over Ethernet/LAN/DTE design -
» [SI-LIST] Re: Intepretation of SPICE Models -
» [SI-LIST] Re: Intepretation of SPICE Models -
» [SI-LIST] AW: Intepretation of SPICE Models -
» [SI-LIST] Intepretation of SPICE Models -
» [SI-LIST] Re: XAUI reference material -
» [SI-LIST] S-paramter to capacitive/inductive crosstalk -
» [SI-LIST] Re: XAUI reference material -
» [SI-LIST] Call for Abstracts -
» [SI-LIST] Re: abt.Tco and Bufferdelay -
» [SI-LIST] Re: abt.Tco and Bufferdelay -
» [SI-LIST] Re: abt.Tco and Bufferdelay -
» [SI-LIST] XAUI reference material -
» [SI-LIST] Re: abt.Tco and Bufferdelay -
» [SI-LIST] Re: abt.Tco and Bufferdelay -
» [SI-LIST] abt.Tco and Bufferdelay -
» [SI-LIST] Re: FW: Re: via capacitance -
» [SI-LIST] Re: PCB Manufacturer Recommendations -
» [SI-LIST] Signal Integrity Engineering Manager Wanted! -
» [SI-LIST] Re: SMA for launching 5-10Gbs signals -
» [SI-LIST] Re: SMA for launching 5-10Gbs signals -
» [SI-LIST] ZBC-2000 dielectric model -
» [SI-LIST] Re: SMA for launching 5-10Gbs signals -
» [SI-LIST] Re: SMA for launching 5-10Gbs signals -
» [SI-LIST] FW: Re: via capacitance -
» [SI-LIST] Re: SMA for launching 5-10Gbs signals -
» [SI-LIST] Re: SMA for launching 5-10Gbs signals -
» [SI-LIST] Re: SMA for launching 5-10Gbs signals -
» [SI-LIST] SMA for launching 5-10Gbs signals -
» [SI-LIST] Re: Translating a Differential IBIS buffer to XTK format -
» [SI-LIST] Re: DDR333 memory module's IBIS model and board file -
» [SI-LIST] Re: via capacitance -
» [SI-LIST] DDR333 memory module's IBIS model and board file -
» [SI-LIST] Translating a Differential IBIS buffer to XTK format -
» [SI-LIST] rise and fall times for SCSI-160 and 320 -
» [SI-LIST] Re: Bibliographies - Write a book? -
» [SI-LIST] -
» [SI-LIST] Re: varying the overlap length between two parallel con ductors -
» [SI-LIST] Re: Multidrop bus with 6 Bidir loads topology and termination -
» [SI-LIST] Re: Board layout issue -
» [SI-LIST] Re: Multidrop bus with 6 Bidir loads topology and termination -
» [SI-LIST] Re: Board layout issue -
» [SI-LIST] Multidrop bus with 6 Bidir loads topology and termination -
» [SI-LIST] Re: Bibliographies -
» [SI-LIST] Fw: SSN -
» [SI-LIST] Re: Signal Integ. / IC Characterization Job Posting -
» [SI-LIST] contests or prize for undergraduate students in signal integrity or EMC -
» [SI-LIST] Bibliographies -
» [SI-LIST] Re: via capacitance -
» [SI-LIST] Was : IBIS Model of 168 Pin SDRAM DIMM Socket -
» [SI-LIST] Re: Board layout issue -
» [SI-LIST] Signal Integ. / IC Characterization Job Posting -
» [SI-LIST] Re: Modeling board contribution to Jitter for 2.5Gb/s Channel -
» [SI-LIST] Re: varying the overlap length between two parallel con ductors -
» [SI-LIST] Re: varying the overlap length between two parallel conductors -
» [SI-LIST] varying the overlap length between two parallel conductors -
» [SI-LIST] Re: Modeling board contribution to Jitter for 2.5Gb/s Channel -
» [SI-LIST] Re: Board layout issue -
» [SI-LIST] Re: still a Hspice segment question -
» [SI-LIST] Re: Current Carrying Capacity -
» [SI-LIST] Apology -
» [SI-LIST] 2003$B%7%9%F%`(BLSI$B5;=QBgA4(B -
» [SI-LIST] VIRUS! was: Re: Your password! -
» [SI-LIST] Modeling board contribution to Jitter for 2.5Gb/s Channel -
» [SI-LIST] Re: Your password! -
» [SI-LIST] Re: Your password! -
» [SI-LIST] add some thing -
» [SI-LIST] still a Hspice segment question -
» [SI-LIST] Re: What's the meaning of "first incident wave"? -
» [SI-LIST] What's the meaning of "first incident wave"? -
» [SI-LIST] Re: Post route analysis in XTK -
» [SI-LIST] Re: Board layout issue -
» [SI-LIST] Board layout issue -
» [SI-LIST] test -
» [SI-LIST] Re: SIGRITY Extends Free Service Offer to SI-LIST Community -
» [SI-LIST] Re: is it posible to remove reflection in a PCB -
» [SI-LIST] ESL component of a SMT resistor -
» [SI-LIST] Re: attention Midwest SI engineers/EMC Symposium attendees also -
» [SI-LIST] Re: SIGRITY Extends Free Service Offer to SI-LIST Community -
» [SI-LIST] Re[2]: about Hspice w element segment ?? -
» [SI-LIST] Re: is it posible to remove reflection in a PCB -
» [SI-LIST] IEC standard on IC pin currents -
» [SI-LIST] is it posible to remove reflection in a PCB -
» [SI-LIST] Re: varying the overlap length between two parallel conductors -
» [SI-LIST] Re: via capacitance -
» [SI-LIST] Re: varying the overlap length between two parallel conductors -
» [SI-LIST] varying the overlap length between two parallel conductors -
» [SI-LIST] attention Midwest SI engineers -
» [SI-LIST] Looking for IBIS model for Pericom 74FCT2253CTW Mux -
» [SI-LIST] Re: length of 10Gig traces on FR4 - compiled responses -
» [SI-LIST] Re: ISI Simulation. -
» [SI-LIST] about Hspice w element segment ?? -
» [SI-LIST] Re: Vih for PCI -
» [SI-LIST] ISI Simulation. -
» [SI-LIST] DesignCon call for papers is now on line -
» [SI-LIST] Re: Vih for PCI -
» [SI-LIST] Recall: Re: Availability of IBIS model of 168 pinSDRAM DIMM so cket -
» [SI-LIST] Recall: Re: Availability of IBIS model of 168 pinSDRAM DIMM so cket -
» [SI-LIST] Re: Availability of IBIS model of 168 pin SDRAMDIM M so cket -
» [SI-LIST] Re: 550 Mbps LVDS Cable and Connector Help -
» [SI-LIST] Re: Question on radiation limits -
» [SI-LIST] Re: Vih for PCI -
» [SI-LIST] Re: Specctraquest Multiboard -
» [SI-LIST] Re: Vih for PCI -
» [SI-LIST] Re: Specctraquest Multiboard -
» [SI-LIST] Re: Question on radiation limits -
» [SI-LIST] Specctraquest Multiboard -
» [SI-LIST] AW: Availability of IBIS model of 168 pin SDRAM DIMM so cket -
» [SI-LIST] AW: Availability of IBIS model of 168 pin SDRAM DIMM socket -
» [SI-LIST] AW: Re: Data bus skew -
» [SI-LIST] AC coupling Capacitors -
» [SI-LIST] 550 Mbps LVDS Cable and Connector Help -
» [SI-LIST] Re: Availability of IBIS model of 168 pin SDRAM DIMM socket -
» [SI-LIST] Re: Data bus skew -
» [SI-LIST] Re: Data bus skew -
» [SI-LIST] Re: Data bus skew -
» [SI-LIST] Data bus skew -
» [SI-LIST] Re: Hspice simulation -
» [SI-LIST] Hspice simulation -
» [SI-LIST] Re: length of 10Gig traces on FR4 -
» [SI-LIST] length of 10Gig traces on FR4 -
» [SI-LIST] Re: Availability of IBIS model of 168 pin SDRAM DIMM socket -
» [SI-LIST] Re: Vih for PCI -
» [SI-LIST] Re: Current Carrying Capacity -
» [SI-LIST] Re: Vih for PCI -
» [SI-LIST] Vih for PCI -
» [SI-LIST] Re: Current Carrying Capacity -
» [SI-LIST] Availability of IBIS model of 168 pin SDRAM DIMM socket -
» [SI-LIST] Fw: TO define the "Preemphasis" -
» [SI-LIST] Re: Receiver End Signal -
» [SI-LIST] Fw: TO define the "Preemphasis" -
» [SI-LIST] Re: Receiver End Signal -
» [SI-LIST] Re: Receiver End Signal -
» [SI-LIST] Receiver End Signal -
» [SI-LIST] Re: testing please ignore -
» [SI-LIST] Re: Current Carrying Capacity -
» [SI-LIST] Re: Current Carrying Capacity -
» [SI-LIST] Current Carrying Capacity -
» [SI-LIST] Re: Question on radiation limits -
» [SI-LIST] Re: Question on radiation limits -
» [SI-LIST] Re: Question on radiation limits -
» [SI-LIST] Re: Question on radiation limits -
» [SI-LIST] Re: Question on radiation limits -
» [SI-LIST] SIGRITY Extends Free Service Offer to SI-LIST Community -
» [SI-LIST] Re: Question on radiation limits -
» [SI-LIST] Re: TO define the "Preemphasis" -
» [SI-LIST] via capacitance -
» [SI-LIST] Re: TO define the "Preemphasis" -
» [SI-LIST] Re: TO define the "Preemphasis" -
» [SI-LIST] Re: TO define the "Preemphasis" -
» [SI-LIST] Re: Speed Limit for dual stripline diff pairs? -
» [SI-LIST] Re: TO define the "Preemphasis" -
» [SI-LIST] Re: TO define the "Preemphasis" -
» [SI-LIST] Re: TO define the "Preemphasis" -
» [SI-LIST] TO define the "Preemphasis" -
» [SI-LIST] How to select the connector under the 3.125Gbps -
» [SI-LIST] Off Topic : JTAG memory read -
» [SI-LIST] Post route analysis in XTK -
» [SI-LIST] varying the overlap length between two parallel conductors -
» [SI-LIST] Re: Peak Current Due to Overshoot -
» [SI-LIST] Re: Speed Limit for dual stripline diff pairs? -
» [SI-LIST] Re: Current carrying cap - microvia -
» [SI-LIST] Re: Speed Limit for dual stripline diff pairs? -
» [SI-LIST] Speed Limit for dual stripline diff pairs? -
» [SI-LIST] Re: Current carrying cap - microvia -
» [SI-LIST] Re: HSPICE model to XTK model -
» [SI-LIST] Re: HSPICE model to XTK model -
» [SI-LIST] HSPICE model to XTK model -
» [SI-LIST] HSPICE W elemnt and 2.5D field solver -
» [SI-LIST] Re: IBIS ECL Clock issue. -
» [SI-LIST] Re: reference plane -
» [SI-LIST] Re: Rectangular patterns on Toplayer. -
» [SI-LIST] Re: reference plane -
» [SI-LIST] Re: IBIS ECL Clock issue. -
» [SI-LIST] Re: IBIS ECL Clock issue. -
» [SI-LIST] Re: IBIS ECL Clock issue. -
» [SI-LIST] Re: IBIS ECL Clock issue. -
» [SI-LIST] IBIS ECL Clock issue. -
» [SI-LIST] Current carrying cap - microvia -
» [SI-LIST] Re: Rectangular patterns on Toplayer. -
» [SI-LIST] Re: a "via" doubt -
» [SI-LIST] a "via" doubt -
» [SI-LIST] Re: Rectangular patterns on Toplayer. -
» [SI-LIST] Re: Rectangular patterns on Toplayer. -
» [SI-LIST] Rectangular patterns on Toplayer. -
» [SI-LIST] Need large bandwidth oscilloscope ? -
» [SI-LIST] Inexpensive, but useful measurement and debugging tools -
» [SI-LIST] Re: IBIS VT & VI curve verification -
» [SI-LIST] Re: IBIS VT & VI curve verification -