Posts for si-list, 06-2002

Browse: Last Month: 05-2002 Main Archive Page Next Month: 07-2002

» [SI-LIST] IBIS VT & VI curve verification -
» [SI-LIST] Re: Book -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, C A; -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, C A; -
» [SI-LIST] Re: Power filtering -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara,C A; -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, CA; -
» [SI-LIST] Re: {SI-LIST] help SGMII -
» [SI-LIST] Re: reference plane -
» [SI-LIST] Re: reference plane -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, CA; -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, CA; -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, CA; -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, CA; -
» [SI-LIST] Re: SI Tools -
» [SI-LIST] Berkeley SPICE buffer models? -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, CA; -
» [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, CA; -
» [SI-LIST] {SI-LIST] help SGMII -
» [SI-LIST] {SI-LIST] help SGMII -
» [SI-LIST] how to decouple this chip (mux and demux ) -
» [SI-LIST] SI Tools -
» [SI-LIST] Post Layout - Thank you so much -
» [SI-LIST] Signal Integrity Manager needed, Santa Clara, CA - [NVIDIA] -
» [SI-LIST] Signal Integrity Manager needed, Santa Clara, CA; -
» [SI-LIST] Re: Power filtering -
» [SI-LIST] Re: AC Termination Question -
» [SI-LIST] Power filtering -
» [SI-LIST] Re: AC Termination Question -
» [SI-LIST] AC Termination Question -
» [SI-LIST] Re: reference plane -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: connectors -
» [SI-LIST] Re: Post Layout Signal Integrity Analysis -
» [SI-LIST] Hi all -
» [SI-LIST] Re: Post Layout Signal Integrity Analysis -
» [SI-LIST] Re: Post Layout Signal Integrity Analysis -
» [SI-LIST] Re: reference plane -
» [SI-LIST] modelling of wire using w-element transmission line -
» [SI-LIST] Re: Post Layout Signal Integrity Analysis -
» [SI-LIST] Re: modelling of wire as w-element transmission line -
» [SI-LIST] Re: modelling of wire as w-element transmission line -
» [SI-LIST] modelling of wires as w-element transmission line -
» [SI-LIST] Re: modelling of wire as w-element transmission line -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Post Layout Signal Integrity Analysis -
» [SI-LIST] Re: Post Layout Signal Integrity Analysis -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Post Layout Signal Integrity Analysis -
» [SI-LIST] Post Layout Signal Integrity Analysis -
» [SI-LIST] Re: [SI-LIST]modelling of wire as w element transmission line -
» [SI-LIST] High Speed Design Class from UC Berkeley -
» [SI-LIST] Re: reference plane -
» [SI-LIST] Re: decoupling capacitors -
» [SI-LIST] Re: reference plane -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] S-I Candidates -
» [SI-LIST] Odd mode impedance -
» [SI-LIST] Re: reference plane -
» [SI-LIST] Re: modelling of wire as w-element transmission line -
» [SI-LIST] Re: Decoupling of diff pair devices -
» [SI-LIST] Re: Odd mode impedance -
» [SI-LIST] Re: connectors -
» [SI-LIST] connectors -
» [SI-LIST] Re: Odd mode impedance -
» [SI-LIST] Re: modelling of wire as w-element transmission line -
» [SI-LIST] Odd mode impedance -
» [SI-LIST] modelling of wire as w-element transmission line -
» [SI-LIST] Re: Asymmetric Coupled Stripline -
» [SI-LIST] Decoupling of diff pair devices -
» [SI-LIST] Asymmetric Coupled Stripline -
» [SI-LIST] AW: Impedence of Differential Pair Not Over Plane (Revised) -
» [SI-LIST] Impedence of Differential Pair Not Over Plane (Revised) -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Parasitic extraction and correlation to package delaymeasurement -
» [SI-LIST] Parasitic extraction and correlation to package delay measurement -
» [SI-LIST] HF return currents + RF energy to EGND = "Hot-box" -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Impedence of Differential Pair Not Over Plane -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: TR0 to text/mathlab converter for HSPICE 2001.4 -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Connexion FPGA-memory -
» [SI-LIST] Connexion FPGA-memory -
» [SI-LIST] decoupling capacitors -
» [SI-LIST] TR0 to text/mathlab converter for HSPICE 2001.4 -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Allegro question. -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: : May 9th Presentation: "Radiation from Edge Effects in Printe... -
» [SI-LIST] Re: Allegro question. -
» [SI-LIST] Re: switching LVDS from loose to tight coupling -
» [SI-LIST] switching LVDS from loose to tight coupling -
» [SI-LIST] Allegro question. -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Re: Ghz/Gbs convert -
» [SI-LIST] Ghz/Gbs convert -
» [SI-LIST] Re: reference plane -
» [SI-LIST] Re: reference plane -
» [SI-LIST] reference plane -
» [SI-LIST] Re: IBIS model ramp option -
» [SI-LIST] IBIS model ramp option -
» [SI-LIST] Re: about split plane -
» [SI-LIST] Re: about split plane -
» [SI-LIST] Re: PCB Processing Comments -
» [SI-LIST] Re: PCB Processing Comments -
» [SI-LIST] Re: si-list Digest V2 #165 -
» [SI-LIST] Re: si-list Digest V2 #165 -
» [SI-LIST] Re: about split plane -
» [SI-LIST] hpsice question -
» [SI-LIST] Re: SV: Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: : May 9th Presentation: "Radiation from Edge Effects in Printe... -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Re: about split plane -
» [SI-LIST] Re: a hspice w-element error -
» [SI-LIST] about split plane -
» [SI-LIST] a hspice w-element error -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Re: SV: Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill --- correction -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] SV: Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Upcoming Classes - Recent Threads -
» [SI-LIST] PRBS Current Model -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] SV: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: SV: Re: Copper Fill --- correction -
» [SI-LIST] SV: Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill --- correction -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Re: Copper Fill -
» [SI-LIST] Copper Fill -
» [SI-LIST] Re: [IBIS Model] Needed Consultant/Expert at generating IBIS models -
» [SI-LIST] Re: 3dB or Knee Frequency -
» [SI-LIST] Re: 3dB or Knee Frequency -
» [SI-LIST] Re: 3dB or Knee Frequency -
» [SI-LIST] IBIS Packaging -
» [SI-LIST] Re: 3dB or Knee Frequency -
» [SI-LIST] Re: 3dB or Knee Frequency -
» [SI-LIST] 3dB or Knee Frequency -
» [SI-LIST] Re: [IBIS Model] Needed Consultant/Expert at generating IBIS models -
» [SI-LIST] Re: rs-485 reflection problem -
» [SI-LIST] rs-485 reflection problem -
» [SI-LIST] Hardware-Guru.com -
» [SI-LIST] [IBIS Model] Needed Consultant/Expert at generating IBIS models -
» [SI-LIST] Job opportunity -
» [SI-LIST] Mutual inductance measurements of voltage drop -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] SI Position/Southern Cal -
» [SI-LIST] Equalization on Receiver -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] Re: Trace Width @ 3Gb/s -
» [SI-LIST] SSTL-2 series terminations -
» [SI-LIST] Trace Width @ 3Gb/s -
» [SI-LIST] SSTL-2 series terminations -
» [SI-LIST] Re: SSTL-2 series termination in DDR Applications -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: unsuscribe si-list -
» [SI-LIST] Re: SSTL-2 series termination in DDR Applications -
» [SI-LIST] unsuscribe si-list -
» [SI-LIST] IBIS conversion -
» [SI-LIST] Job Oppotunities(EMI/EMC engineer, SAIT) -
» [SI-LIST] Re: 2 kV Capacitor -
» [SI-LIST] Re: SSTL-2 series termination in DDR Applications -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Questions Concerning BGA Mounting -
» [SI-LIST] Re: Questions Concerning BGA Mounting -
» [SI-LIST] Questions Concerning BGA Mounting -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Re: PCIX A/D WIDTH Min -
» [SI-LIST] PCIX A/D WIDTH Min -
» [SI-LIST] Re: SMA connectors -
» [SI-LIST] SMA connectors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Impedance of Interconnect -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Re: SSTL-2 series termination in DDR Applications -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] SSTL-2 series termination in DDR Applications -
» [SI-LIST] 2 kV Capacitor -
» [SI-LIST] Decoupling of HSTL Vref -
» [SI-LIST] Re: Com port -
» [SI-LIST] Re: Com port -
» [SI-LIST] Re: Com port -
» [SI-LIST] Com port -
» [SI-LIST] Re: DDR SSTL-2 Signal Terminations -
» [SI-LIST] Re: DDR SSTL-2 Signal Terminations -
» [SI-LIST] DDR SSTL-2 Signal Terminations -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Decoupling capacitors -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Re: Using W-element in HSPICE -
» [SI-LIST] Re: I-V vs V-T endpoints In IBIS -
» [SI-LIST] helical antenna for GPS -
» [SI-LIST] where can i find a book describe the details of the v-i and v-t curves -
» [SI-LIST] commands: -
» [SI-LIST] SIGRITY Offers Free Service to SI-LIST Community -
» [SI-LIST] Re: I-V vs V-T endpoints In IBIS -
» [SI-LIST] Re: I-V vs V-T endpoints In IBIS -
» [SI-LIST] Re: PCB stack up -
» [SI-LIST] New Errata Sheet for Wadell's "Transmission Line Design Handbook" -
» [SI-LIST] I-V vs V-T endpoints In IBIS -
» [SI-LIST] Re: Errata Sheet for Wadell's "Transmission Line Design Handbook" -
» [SI-LIST] Re: PCB Stackup -