[SI-LIST] Re: Determining timing budgets using IBIS

So the fact that IBIS doesn't model delays is really no disadvantage as
compared to SPICE models?

It seems that some of the larger companies I worked for preferred SPICE
models for board level timing. Of course those are the companies that have
resources to perform detailed simulation and vendors are more likely to
supply them with SPICE models.

Perhaps someone could list the pros and cons for each type of model.

I'm in a situation where my tool budget is limited, so I reasoned that I
would be better off converting an IBIS model to spice so I can use some of
the lower cost SPICE simulators. Any hazards to look out for when using this
method?


Thanks



----- Original Message -----
From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxx>
To: <alexh1@xxxxxxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Sent: Monday, July 29, 2002 5:59 AM
Subject: [SI-LIST] Re: Determining timing budgets using IBIS


> Also note that this is no different when you have SPICE models.
>
> I have never seen a SPICE model for an ASIC output buffer that includes
> everything from the clock on out.  Even with older MSI ICs, often their
> SPICE models modeled the input receivers or output buffers only, and not
> the guts on the chip.  You couldn't use them for clock-to-out timing
> measurements.
>
> Andy
>
>
>
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