[SI-LIST] Re: via capacitance
- From: "Istvan Novak" <istvan.novak@xxxxxxxxxxxxxxxx>
- To: <howiej@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 17 Jul 2002 08:02:47 -0400
Dear Dr. Johnson,
Thanks for posting from your upcoming book, I look forward to seeing it in
print.
I offer the following comments on the posted pages:
1., I am sure you address this point somewhere in your upcoming book, just
to make sure that si-list members can put the posted pages properly into
context: vias, like any other interconnects, are inherently associated with
some capacitance, inductance, resistance. This is fact of nature, and not
necessarily bad. In a lossless interconnect, they set the characteristic
impedance as Zo=sqrt(L/C) and the propagation delay as tpd=sqrt(L*C). On a
matched trace, we dont need to worry about any large amount of trace
capacitance or trace inductance, as long as the Zo and tpd numbers are
acceptable. The same applies to vias and through holes: if the entire
length of the barrel carries the signal (we make the tranition between the
two outer layers) our only goal is to set the equivalent inductance and
capacitance of the via to create a characteristic impedance that matches the
characteristic impedance of the connecting traces. One good article showing
techniques to achieve this is: Danial G.Swanson, "Optimising Transitions in
Multilayer PC Boards," Proceedings of Workshops at IEEE MTTS, 11-16 June,
2000, Boston, MA.
What really matters for high-speed signaling purposes is the deviation from
this ideal situation. This can happen in two ways: the via impedance may
not match the trace impedance, or not the entire length of the via carries
the signal (or a combination of these two). In the first case, having a via
between the outer two layers, the equivalent via impedance typically may be
lower than the characteristic impedance of connecting traces. This creates
an extra capacitance of the via, but only the DIFFERENCE (and not the entire
via capacitance) causes reflection losses in high-speed signaling. For
instance, having 50-ohm traces and a 100-mil thick FR4 board, the
capacitance of a 50-ohm matched through via between the outer layers is
approximately 0.36pF. If the estimated via capacitance is 0.5pF, only
0.5-0.36=0.14pF lumped capacitance needs to be taken into account in
simulating the via-loading effects. If we want to account for the
additional 0.36pF in the simulations, we should do that by inserting a
Zo=50-ohm tpd=18ps delay line in series to the traces. In this first case
obviously we cannot reduce the via capacitance by back drilling. In the
second case, when there is a through via, but the signal transition is not
between the outer two layers, the entire static capacitance of the 'UNUSED'
portion of the via (also called via stub) shows up as capacitive loading.
In this second case backdrilling helps.
2., In the text, the via shown in Figure 5.25 is called 'blind via'. In my
understanding, blind vias are those, which connect from one of the surface
layers down to one of the inner layers, so on the finished board we have
access to only one end of it, but not to the other end. By using this
definition, the via shown in Figure 5.25 is a through via. On the other
hand, if it was really a blind via, just additional layers on one side of
the stackup are not shown in the figure, those layers not shown would have
an impact (increase) on the reported capacitance figures.
3., On page 5.2, in the description of the three possible ways to reduce via
capacitance, the first item is called blind via. It appears to me that the
description refers to a buried via process. In my understanding, the
differentiator is: if the via hole is made BEFORE final lamination, it means
that it will end up being between inner layers at both of its ends, so none
of the via ends is accessible or visible on the finished board. Certainly it
would be possible to create a blind via before the final lamination step,
but because the extra processing step would add cost unnecessarily, I do not
see a reason for doing this unless the blind via must have a large aspect
ratio (>1) that cannot be plated if created after lamination.
Best regards
Istvan Novak
SUN Microsystems
----- Original Message -----
From: "Dr. Howard Johnson" <howiej@xxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, July 16, 2002 12:45 AM
Subject: [SI-LIST] Re: via capacitance
>
> Oops! I apologize for thoughtlessly sending an attachment in
> my
> missive dated Thursday, 11 July about via capacitance.
> If you are interested, the attachment
> has been posted to:
> www.sigcon.com/pubs/news/viacapacitance.pdf
>
> Best regards,
> Dr. Howard Johnson, Signal Consulting Inc.,
> tel +1 509-997-0505, howiej@xxxxxxxxxx
> http:\\sigcon.com -- High-Speed Digital Design articles,
> books, tools, and seminars
>
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