Also note that this is no different when you have SPICE models. I have never seen a SPICE model for an ASIC output buffer that includes everything from the clock on out. Even with older MSI ICs, often their SPICE models modeled the input receivers or output buffers only, and not the guts on the chip. You couldn't use them for clock-to-out timing measurements. Andy ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu