[SI-LIST] Re: GTL buffers Vref
- From: "Grigoras, Adrian C" <adrian.c.grigoras@xxxxxxxxx>
- To: "'Gupta, Naveen'" <naveen@xxxxxxxxx>
- Date: Fri, 30 Aug 2002 11:05:24 -0700
Then it looks like you might have case of high side ringback if better
margins are when Vref is lower.
there are several things you can try :
*make sure the GTL bus is terminated at the end of the bus - most likely
cause and the CORRECT spec values is applied - i.e. turn ON the compensation
circuitry if exists :-)
*identify the failing bit and make sure the layout guidelines were
implemented correctly.
*verify edge rates to be within the spec (@ driver and receiver)
When Vref margins are better if Vref is higher , low side ringback is likely
the case here :
* make sure the NMOS compensation works properly -
* layout guidelines
* edge rates
This is a very generic answer to very generic question :-)
-----Original Message-----
From: Gupta, Naveen [mailto:naveen@xxxxxxxxx]
Sent: Friday, August 30, 2002 10:56 AM
To: 'adrian.c.grigoras@xxxxxxxxx'
Subject: RE: [SI-LIST] Re: GTL buffers Vref
Adrian,
Thanks for your answer.
They are obtained at preliminary system validation.
Thanks,
Naveen
-----Original Message-----
From: Grigoras, Adrian C [mailto:adrian.c.grigoras@xxxxxxxxx]
Sent: Friday, August 30, 2002 10:54 AM
To: Gupta, Naveen; 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: GTL buffers Vref
Can you please define "better results" ?
Are they obtained in simulation or design validation ?
-----Original Message-----
From: Gupta, Naveen [mailto:naveen@xxxxxxxxx]
Sent: Friday, August 30, 2002 10:46 AM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] GTL buffers Vref
Hi all,
I have a basic question about the Vref for GTL input buffers.
If the Vref spec states a 1.0 Volts, but better results are obtained
at a lower voltage, what should be the issues one should examine.
Relatedly, if better results in turn are obtained at a higher voltage,
then what
should one examine?
Thanks for your answers.
Thanks,
Naveen
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