[SI-LIST] Eye pattern between QDR and FPGA
- From: "Ibrahim Khan" <ikhan@xxxxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 8 Aug 2002 11:13:17 -0500
SI Gurus,
I need to exercise a 32 bit data bus between a QDR and an FPGA. The
data is HSTL running at 166Mhz clocked on both edges. Do I need to run
a PRBS stream on every line from FPGA to look at the eye pattern?.
Anybody has a code to generate a PRBS pattern in FPGA.
Thanks
Ibrahim Khan
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