[SI-LIST] Re: Inter Symbol Interference

Alex,

Couple of possibilities to your problems:

1) Due to ISI.  The ISI is due to different signal 
patterns in your data/address bus 
(e.g. 1010001010100001111010) VS.
clock pattern of 1010101010. The data/address will have 
different initial conditions (e.g. voltage level) before 
the data/address  bus switching (sometime data/address have
enough time to settle to hi/lo steady state before
next switching happens, sometimes don't). If the initial 
conditions are different, the time takes data/address to 
switching  from initial logic level to the logic threshold 
will be different. 

2) Due to output buffer rise/fall time mismatch.
The rise/fall time mismatch between clock and data/address
can also impact you timing.

3) Different loading/topology for clock and data/address
   That can introduce different impedance mismatch /reflection ..

4) ...


Couple of suggestions:

1) If you have choice, select the right I/O buffers can reduce 
timing jitters due to ISI and rise/fall mismatch.

2) Use right termination, to reduce ISI.  Parallel 
   termination Rp (=Z0) to VTT may be a good choice 
   which will reduce the max voltage swing so that
   the initial switching level be more unified, and
   ISI can be reduced.  Of course, the noise margin
   will be reduced.  



   Let me know if I can be further helps.



  Thanks!



  Bill Chen, Ph.D.
  
  Andiamo Systems Inc
 

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Alexander Rose
Sent: Tuesday, August 27, 2002 8:22 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Inter Symbol Interference



I'm seeing a very interesting phenomenon in a spice simulation where a 
250MHz LVCOMOS (1.8V) clock using a 35ohm driver, is FASTER by nearly .5
ns 
in the worst (slow) case.  This is wrecking havoc in my timing budget
since 
the clock doesn't track address and data in the same way between worst
case 
and best case creating an impossible window. We believe the problem is 
inter symbol interference (ISI) and we only see this problem occur once
the 
clock reaches a steady state (several cycles into the simulation).  Can 
someone explain what causes this occur, and the best way to combat it?

Thanks,
Alex

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