[SI-LIST] Re: Inter Symbol Interference
- From: "john lipsius" <johnlipsius@xxxxxxxxx>
- To: <arose@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 27 Aug 2002 13:15:39 -0700
Alex,
Change one thing at a time. I haven't really seen this with just a single net
like
you present.
But, here's my 2 cents...
1. If you're looking at the far end of an interconnect with those results I
would do a run with only a reference load (R and C to gnd or just R) and
see any difference. If so, I would inspect your interconnect model with
some other well known driver model.
2. Driver or rcvr pkg models could be causing this (RC behavior at faster
edges),
or other lumped elements in the spice circuit you may not know are there.
3. Driver model could be bad or the way it's parametrized. There also
could be some accurate or inaccurate effect of VDD inductance causing
switching pushout for fast case that's greater than that for slow, or just a
greater factor than slow case switching.
-John
----- Original Message -----
From: "Alexander Rose" <arose@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, August 27, 2002 8:21 AM
Subject: [SI-LIST] Inter Symbol Interference
>
> I'm seeing a very interesting phenomenon in a spice simulation where a
> 250MHz LVCOMOS (1.8V) clock using a 35ohm driver, is FASTER by nearly .5 ns
> in the worst (slow) case. This is wrecking havoc in my timing budget since
> the clock doesn't track address and data in the same way between worst case
> and best case creating an impossible window. We believe the problem is
> inter symbol interference (ISI) and we only see this problem occur once the
> clock reaches a steady state (several cycles into the simulation). Can
> someone explain what causes this occur, and the best way to combat it?
>
> Thanks,
> Alex
>
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