[SI-LIST] Inter Symbol Interference

I'm seeing a very interesting phenomenon in a spice simulation where a 
250MHz LVCOMOS (1.8V) clock using a 35ohm driver, is FASTER by nearly .5 ns 
in the worst (slow) case.  This is wrecking havoc in my timing budget since 
the clock doesn't track address and data in the same way between worst case 
and best case creating an impossible window. We believe the problem is 
inter symbol interference (ISI) and we only see this problem occur once the 
clock reaches a steady state (several cycles into the simulation).  Can 
someone explain what causes this occur, and the best way to combat it?

Thanks,
Alex

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