[SI-LIST] Inter Symbol Interference
- From: Alexander Rose <arose@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 27 Aug 2002 08:21:39 -0700
I'm seeing a very interesting phenomenon in a spice simulation where a
250MHz LVCOMOS (1.8V) clock using a 35ohm driver, is FASTER by nearly .5 ns
in the worst (slow) case. This is wrecking havoc in my timing budget since
the clock doesn't track address and data in the same way between worst case
and best case creating an impossible window. We believe the problem is
inter symbol interference (ISI) and we only see this problem occur once the
clock reaches a steady state (several cycles into the simulation). Can
someone explain what causes this occur, and the best way to combat it?
Thanks,
Alex
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
