[SI-LIST] Re: Output Capacitor of a switching Regulato

  • From: ANAND KURIAKOSE <Anand.Kuriakose@xxxxxxxxxx>
  • To: vel_ss@xxxxxxxxx
  • Date: Thu, 1 Aug 2002 21:01:23 -0700

        Hi Senthil,

        Basically what i am doing is substituting VL/Lo in place of di/dt in
the equation, where VL is the smallest of the voltages across the output
inductor and Lo is the output inductor value.  And this is what the
switching regulator's datahseet also says and this puts us in a safe Cmin.
The design is for the chipset and the chipset manufacturer hasnt specified
the di/dt specification. 

        Regards,
        Anand.




        From:   Senthil S Velmurugan <vel_ss@xxxxxxxxx> on 08/02/2002 01:00
AM
        Please respond to vel_ss@xxxxxxxxx@SMTP@Exchange
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        Subject:        [SI-LIST] Re: Output Capacitor of a switching
Regulato


        Hi Anand,
        Can you let me know how you have arrived at di/dt
        value for the equation ?
        I see, say, some CPU's requirement for X-Amp/uS
        How much you want to have VRM or switcher bulk cap to
        supply those X-Amp/uS ?.
        I think the X-Amps is supplied by a combination of
        package, plane and decoupling caps and
        bulk cap follows to fill those,  At what rate is my 
        question in other way.

        Hi Larry,
        I think this need to be clarified to calculate Cmin,
        but I do not see any info on this subject other than
        using a tool(ex,. Ansoft)to model the complete
        switcher
        with package parasitic of CPU which you may not know
        unless you use TDR to extract those parameters, 
        these models are not given out by any CPU vendor. 
        Tools to reduce plane impedance are being used to
        reduce the plane impedance below Z target by choosing
        an huge array of caps. Caveat being, What is the roll
        up of impedance curve at what frequency depends on the
        processor's working pattern and freq'y, this pattern
        needs to be known to reduce the amount of caps
        suggested by the tool.

        Can you through some more light on this and a suggest
        an optimum way to ensure right Bulk cap for a on board
        regulator in the first time without doing any
        simulation or without building the board and measure
        it approach. 

        VRM modules have the luxury of holding 10 caps on a
        vertical board but not on a small form factor embedded
        mother boards is another challenge and no room to have
        liberal approach.

        Thanks
        Senthil

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