[SI-LIST] Re: Output Capacitor of a switching Regulato

  • From: Larry Smith <Larry.Smith@xxxxxxx>
  • To: si-list@xxxxxxxxxxxxx, vel_ss@xxxxxxxxx
  • Date: Fri, 2 Aug 2002 09:37:39 -0700 (PDT)

Senthil - the equations discussed in this thread are sufficient to
calculate the capacitance and ESR required to go with a switching
regulator with a specified di/dt, at least to within a factor of 2.  A
more accurate answer will require a detailed analysis of all the
packaging parasitics involved and the specific nature of the regulation
loop.

The switching regulator supplier will usually state the di/dt
capability of his product.  If not, it can be roughly estimated by the
head voltage minus the output voltage and the value of the working
inductance.  V = L di/dt .  Add in some time for the loop to respond,
it will not happen immediately.

In frequency domain terminology, the capacitance maintains the power
distribution system impedance in a certain frequency range.  Our
calculation ensures that there is overlap between the low frequencies
that the regulator covers (DC to perhaps 100 kHz) and the middle
frequencies that the bulk capacitors cover (100 kHz to 1 MHz,
roughly).  High frequency ceramic capacitors are required for
frequencies above approximately 1 MHz up to a frequency which is
limited by the inductance of the mounting structure and package that
contains the power consuming silicon.

In time domain terminology, the bulk capacitor must deliver current
long enough for the regulation loop to detect that a current transient
has taken place and ramp up the inductor current to supply that current
transient.  The calculations that we have made use the time domain
approach.  Similar calculations can be made in the frequency domain and
give the same capacitance.

regards,
Larry Smith
Sun Microsystems

> Delivered-To: si-list@xxxxxxxxxxxxx
> Date: Thu, 1 Aug 2002 11:30:18 -0700 (PDT)
> From: Senthil S Velmurugan <vel_ss@xxxxxxxxx>
> Subject: [SI-LIST] Re: Output Capacitor of a switching Regulato
> To: si-list@xxxxxxxxxxxxx
> MIME-Version: 1.0
> Content-Transfer-Encoding: 8bit
> X-Approved-By: Raymond.Anderson@xxxxxxx
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> X-original-sender: vel_ss@xxxxxxxxx
> X-list: si-list
> 
> 
> Hi Anand,
> Can you let me know how you have arrived at di/dt
> value for the equation ?
> I see, say, some CPU's requirement for X-Amp/uS
> How much you want to have VRM or switcher bulk cap to
> supply those X-Amp/uS ?.
> I think the X-Amps is supplied by a combination of
> package, plane and decoupling caps and
> bulk cap follows to fill those,  At what rate is my 
> question in other way.
> 
> Hi Larry,
> I think this need to be clarified to calculate Cmin,
> but I do not see any info on this subject other than
> using a tool(ex,. Ansoft)to model the complete
> switcher
> with package parasitic of CPU which you may not know
> unless you use TDR to extract those parameters, 
> these models are not given out by any CPU vendor. 
> Tools to reduce plane impedance are being used to
> reduce the plane impedance below Z target by choosing
> an huge array of caps. Caveat being, What is the roll
> up of impedance curve at what frequency depends on the
> processor's working pattern and freq'y, this pattern
> needs to be known to reduce the amount of caps
> suggested by the tool.
> 
> Can you through some more light on this and a suggest
> an optimum way to ensure right Bulk cap for a on board
> regulator in the first time without doing any
> simulation or without building the board and measure
> it approach. 
> 
> VRM modules have the luxury of holding 10 caps on a
> vertical board but not on a small form factor embedded
> mother boards is another challenge and no room to have
> liberal approach.
> 
> Thanks
> Senthil
> 
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