[SI-LIST] Re: Placement of Decoupling Caps
- From: Ray Anderson <Raymond.Anderson@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 2 Aug 2002 09:49:28 -0700 (PDT)
Ibrahim wrote:
>
>Ray,
>Thanks for taking time to educate people. I have question on your
>following comments:
>
>"Now assume you are decoupling a high frequency processor running at 1
>GHz. Say you chose a decap that resonates at 1GHz."
>
>Question is tha:
>1. Is there a relationship between the processor running at 1GHz and
>the decap resonating at 1GHz
We select decoupling capacitors whose series resonant frequencies
are such that the superposition of the impedance profiles of the
numerous caps form a composite impedance profile whose magnitude
is below a certain calculated target impedance.
A PDS (Power Distribution System) contains various elements that
contribute to the total impedance profile. At low frequencies
the VRM output impedance is the dominating factor up to say several
hundred KHz. Above that bulk capacitors take over up to perhaps
a MHz or so. From that frequency up to about 100 MHz or so the
ceramic decaps determine the impedance profile. Above a a 100 MHz
or so, the interplane capacitance of the power planes becomes the
predominant source of decoupling up to the GHz region. The exact
frequencies quoted above are approximate and fuzzy, but serve to
illustrate the trend. The various impedances presented by the
various mechanisms kind of blur into each other at the transition
points to create a continuum from "DC to Daylight" so to speak.
My example might have been a little misleading. As it turns out
the decoupling caps utilized to create the composite impedance
profile that I just mentioned usually have resonant frequencies
from a few MHz to say a couple hundred MHz. Above a few hundred
MHz, the interplane capacitance takes over and is effective into
the GHz. At spot frequencies (say buss frequencies, clock frequencies
and harmonics thereof etc.) above a 100 MHz or so, small decaps can
be chosen to target these spot frequencies for EMI purposes.
So the example of a decap resonanting a 1 GHz was little extreme.
It might be hard to find a decap that really resonates that high.
Also note that high frequencies inside a processor or ASIC package
are isolated from the effects of on board decoupling by the low
pass nature of the package. Effective decoupling of the silicon
quite often depends on package and chip level decoupling. No matter
how well a PCB might be decoupled, the isolating effect of the package
prevents much of the current provided by the PCB decoupling capacitors
from being available to the current sinking silicon at the rates at
which it needs to be supplied, hence the need for decoupling on
the silicon side of the package parasitics.
>2. How do we find the resonance frequecny of a cap
The resonant frequency of a decap is a function of three
things: The capacitors capacitance, the parasitic inductance
inside the capacitors package, and the mounting inductance
contributed by the pads, escapes, vias and planes. This is
very geometry dependent.
Given that you know the values of the C and L's then you can
easily calculate the resonant frequency: Fo= 1/(2*pi*sqrt(LC))
Or you could measure the SRF in the lab on a test board utilizing
a VNA.
>
>Thanks for your time.
>Regards
>Ibrahim Khan
Hope that helps out.
-Ray Anderson
Sun Microsystems Inc.
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