[SI-LIST] AW: Re: DDR-II: SSTL_18 & ODT
- From: hermann.ruckerbauer@xxxxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 14 Aug 2002 09:04:45 +0200
Hi,
two comments:
Up to now there is no final SSTL18, but there will be a SSTL18 =
eventually!
And it is correct, that the ODT values are some compromise between =
Power and
SI. But there are some more thoughts.
First the problem is, that (usually) read data sees different topology =
then write=20
data (expect e. g. a star bus topology). So optimization for read is =
very often=20
worse for write.=20
In cas of ODT and DDRII the topology for a two slot system is some kind =
of asymetric
T bus. E. g. the LeadIn on Mobo is 40 Ohm and on the DIMM you do have a =
20 Ohm Stub
resistor in series with a 55 Ohm trace. For the Write in a two slot =
system, the data sees
a 40 Ohm trace, and then 20 + 55 ohm in parallel with the second slot =
(20 + 55 ohm).=20
If you are calculating this one, the branch is not to bad matched.=20
And for the 20 + 55 Ohm the 75 Ohm is not the worst termination for the =
second slot.
In case of a single Slot system the termination of DDRII is done on the =
same slot, that is=20
written to (of course, as there is only one slot poplated). To burn not =
to much power, the
termination is only half of the 2 Slot system. This can be done, as for =
a single slot
population the SI is not as bad as for the dual slot system.
So this is one of the tradeoffs between SI and Power, that Gregory =
mentioned=20
regards
Hermann
-----Urspr=FCngliche Nachricht-----
Von: pgregory [mailto:pgregory@xxxxxxxxxx]
Gesendet am: Dienstag, 13. August 2002 23:38
An: 'si-list@xxxxxxxxxxxxx'
Betreff: [SI-LIST] Re: DDR-II: SSTL_18 & ODT
JEDEC has two SSTL specs: SSTL_2 (2.5V) [JESD8-9B] and SSTL_3 (3.3V).
There is no SSTL_1 or SSTL_18 JEDEC spec. =20
The HSTL spec is a 1.5V spec [JESD8-6]. The industry has created a=20
defacto standard for HSTL operating at 1.8V (see Micron RLDRAM and=20
QDRII data sheets=20
http://download.micron.com/pdf/datasheets/sram/MT54W1MH18B_4.pdf )
On-die-termination has to balance many things including power and
SI. The non-ideal termination is a compromise. See=20
http://download.micron.com/pdf/technotes/TN4606.pdf for a look=20
at some comparison values.
-----Original Message-----
From: Bret Stott [mailto:bstott@xxxxxxxxxxxxxxxx]
Sent: Monday, August 12, 2002 12:35 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR-II: SSTL_18 & ODT
Hi SI-gurus,
I am a new member of this list and I have a few questions about DDR-II =
that
I=20
was hoping someone could help me out with. Currently, I don't have =
access
to=20
JEDEC so most of my information is from alternate sources such as the
Samsung=20
DDR-II spec.
o Can anyone point me at a SSTL_18 specification?
o Can someone help me understand the on-die-termination strategy for =
DDR-II?
Why are the values 75 & 150 Ohms? What electrical topology is being
assumed?
o My initial analysis suggests that it is possible to use class I =
drivers
for=20
the address bus (5 load) and also for a point-to-point data bus. The =
data
bus=20
may require some non-standard termination values though. Does anyone =
have
any=20
information that supports of refutes this?
Thanks in advance,
-Bret
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