[SI-LIST] Matched Length Constaint Approximation for a bus running between 20-50MHz
- From: Adeel Malik <AdeelM@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 16 Aug 2002 17:14:08 +0500
Hi All,
In order to accurately calculate the maximum lenght difference to
meet the setup and hold times among the bus signals (address, control and
data) , one needs to find the flight time of the traces, clock-to-output
delay of the Flip-Flops and other logic involved ,cycle-time period and
other things......
But if someone is designing the bus for a 20-50MHz range, I don't think that
there is any need to precisely calculate all the afore-mentioned parameters
because I know that the cycle-time period for a bus running at e.g 50MHz is
about 20ns while the delay of the outer-layer PCB Track is about 150 ps/inch
and clock to output delay of the flip-flop in the memory is about 1-2ns
leaving at least 10-15ns of time-margin. So can someone give me any crude
approximation to determine the maximum lenght difference among the
microstrip traces running in 20- 50MHz range.
Regads,
ADEEL MALIK,
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