Date Index for si-list, 07-2003

[si-list] || [07-2003 Date Index] [07-2003 Thread Index]

[SI-LIST] need advice on books - karan bagga
[SI-LIST] Re: need advice on books - Abdulrahman Rafiq
[SI-LIST] Re: how to model an oscillator ? - Ingraham, Andrew
[SI-LIST] How to control CMOS circuit¡¯s stage-stage DC bias voltage variation with process variation? - Bi Han
[SI-LIST] IBIS Interconnect Modeling Specification - Request for Feedback - Mirmak, Michael
[SI-LIST] via teardropping effect on signal integrity? - Ivor Bowden
[SI-LIST] Re: via teardropping effect on signal integrity? - mkhusid
[SI-LIST] Re: via teardropping effect on signal integrity? - Pat Diao
[SI-LIST] Re: via teardropping effect on signal integrity? - cadpro2k
[SI-LIST] Re: via teardropping effect on signal integrity? - Scott McMorrow
[SI-LIST] Re: via teardropping effect on signal integrity? - Scott McMorrow
[SI-LIST] resistor array compact PCI signals - Nico Fleurinck
[SI-LIST] rapid io tracking/termination impedance - WALKER, Mark
[SI-LIST] SPI-4 interface - Patrick Jabbaz
[SI-LIST] Re: SPI-4 interface - mkhusid
[SI-LIST] Re: SPI-4 interface - Tom Biggs
[SI-LIST] Re: via teardropping effect on signal integrity? - Guasti Giovanni
[SI-LIST] Re: resistor array compact PCI signals - Richard . Litt
[SI-LIST] Re: via teardropping effect on signal integrity? - Ivor Bowden
[SI-LIST] measuring internal signals on a chip - Doug Smith
[SI-LIST] Re: how to model an oscillator ? - Jack Stone
[SI-LIST] 8 Layer stack up - Nagaraj
[SI-LIST] Inclusion of RLGC package info in IBIS - R, Granthana
[SI-LIST] Re: how to model an oscillator ? - Ingraham, Andrew
[SI-LIST] Re: rapid io tracking/termination impedance - Steve Horne
[SI-LIST] Re: 8 Layer stack up - Ravinder . Ajmani
[SI-LIST] Marshall Sherfield Fellowship - lin shen
[SI-LIST] Re: 8 Layer stack up - Mehrdad Salami
[SI-LIST] Re: need advice on books - Farzad Ebrahimi
[SI-LIST] Re: 8 Layer stack up - Ravinder . Ajmani
[SI-LIST] si-list is back in business - Ray Anderson
[SI-LIST] Differential bus emission - Dorin
[SI-LIST] Re: si-list is back in business - Ken Cantrell
[SI-LIST] Re: Differential bus emission - Lee Ritchey
[SI-LIST] [Freelists News] crippling outage, partial recovery - Ray Anderson
[SI-LIST] How many Ground pins are enough - Ravinder . Ajmani
[SI-LIST] Field Solver Questions - Sainath Nimmagadda
[SI-LIST] Re: 8 Layer stack up - Best, Frederick K
[SI-LIST] Regulatory testing - Martin Euredjian
[SI-LIST] Re: Regulatory testing - Lfresearch
[SI-LIST] How many Ground pins are enough - Ravinder . Ajmani
[SI-LIST] Fwd: vgs stress in digital cmos process - Bi Han
[SI-LIST] Re: Regulatory testing - Michael Poimboeuf
[SI-LIST] Re: Regulatory testing - EVANS,JEFF (HP-Cupertino,ex3)
[SI-LIST] IBIS models for RC Network - Suresh.K
[SI-LIST] Field Solver Questions - Geoff Stokes
[SI-LIST] LVDS Routing - Mehrdad Salami
[SI-LIST] Re: si-list Digest V3 #186 - Thomas Beneken
[SI-LIST] Recommendation for high-speed digital input protection? - JP Nicholls
[SI-LIST] Re: Recommendation for high-speed digital input protection? - Tom Biggs
[SI-LIST] Re: Fwd: vgs stress in digital cmos process - Christopher Jakubiec
[SI-LIST] Re: Fwd: vgs stress in digital cmos process - Robert Kezer
[SI-LIST] Re: Fwd: vgs stress in digital cmos process - Christopher Jakubiec
[SI-LIST] Re: LVDS Routing - Gupta, Deepali
[SI-LIST] Re: Fwd: vgs stress in digital cmos process - Robert Kezer
[SI-LIST] Free webinar on translating SPICE models to IBIS - Lynne Green
[SI-LIST] Re: 8 Layer stack up - Youssef Khalife
[SI-LIST] Crystal Oscillator - pankaj kumar
[SI-LIST] Measuring Crosstalk - chandaharitha
[SI-LIST] Re: 8 Layer stack up - Best, Frederick K
[SI-LIST] Re: Measuring Crosstalk - Jon Powell
[SI-LIST] paper on 9ps high-resolution TDR - Schoen, Kipp
[SI-LIST] Re: Measuring Crosstalk - Bob Patel
[SI-LIST] Question on DDR SDAM timing spec - Chris Cheng
[SI-LIST] Lumped Vs Distributed Model - chandaharitha
[SI-LIST] please help me defining a problem - karan bagga
[SI-LIST] can a open drain pin drive high impedance? - hariharan
[SI-LIST] AW: Question on DDR SDAM timing spec - hermann . ruckerbauer
[SI-LIST] what is the max trace length for the signals adjecent to the power planes. - Pushpraj Adhage
[SI-LIST] Via anti-pad on 2G signaling - chris . mcgrath
[SI-LIST] Re: Question on DDR SDAM timing spec - Steve Horne
[SI-LIST] Problems auto unsubbing from list - Mark Randol
[SI-LIST] How many Ground pins are enough - Ravinder . Ajmani
[SI-LIST] Re: Question on DDR SDAM timing spec - Jonathan Dowling
[SI-LIST] FW: Field Solver Questions - Sainath Nimmagadda
[SI-LIST] Re: Question on DDR SDAM timing spec - Chris Cheng
[SI-LIST] Re: Reducing SSO noise in an FPGA - bpanos
[SI-LIST] Re: Reducing SSO noise in an FPGA - Scott McMorrow
[SI-LIST] Re: Reducing SSO noise in an FPGA - bpanos
[SI-LIST] [Fwd: Re: Re: Reducing SSO noise in an FPGA] - Scott McMorrow
[SI-LIST] Re: Reducing SSO noise in an FPGA - Chris Cheng
[SI-LIST] Re: Reducing SSO noise in an FPGA - bpanos
[SI-LIST] Drivers-Receivers in DSM technologies - manthos labropoulos
[SI-LIST] Differential traces in ebd file - V S
[SI-LIST] Need Signal Integrity engineer ASAP - Kevin Pierpoint
[SI-LIST] Re: How many Ground pins are enough - Rich Peyton
[SI-LIST] Re: Reducing SSO noise in an FPGA - Ken Cantrell
[SI-LIST] Re: Differential traces in ebd file - Muranyi, Arpad
[SI-LIST] Re: Reducing SSO noise in an FPGA - Bradley S Henson
[SI-LIST] DESIGNCON 2004 CALL FOR PAPERS - Ozgur Misman
[SI-LIST] Re: Question on DDR SDAM timing spec - Eric Deys
[SI-LIST] Re: Differential traces in ebd file - V S
[SI-LIST] extraction tool - houfei chen
[SI-LIST] Re: extraction tool - Scott McMorrow
[SI-LIST] Re: Lumped Vs Distributed Model - john lipsius
[SI-LIST] Re: Question on DDR SDAM timing spec - john lipsius
[SI-LIST] Re: Question on DDR SDAM timing spec - Allan Davidson
[SI-LIST] Re: Question on DDR SDAM timing spec - Jonathan Dowling
[SI-LIST] IEEE CPMT Society Phoenix Chapter - Aug 2003 meeting announcement - Sam Karikalan
[SI-LIST] RMCEMC July meeting announcement - Charles Grasso
[SI-LIST] AIC7899 pci SCSI controller - karan bagga
[SI-LIST] op-amp compensation capacitor in digital cmos process - Bi Han
[SI-LIST] topology for memory bus - karan bagga
[SI-LIST] Re: Reducing SSO noise in an FPGA - Fabrizio Zanella
[SI-LIST] Re: Reducing SSO noise in an FPGA - Bradley S Henson
[SI-LIST] Re: Reducing SSO noise in an FPGA - Jon Powell
[SI-LIST] Re: Reducing SSO noise in an FPGA - Scott McMorrow
[SI-LIST] Re: Reducing SSO noise in an FPGA - Chris Cheng
[SI-LIST] Re: op-amp compensation capacitor in digital cmos process - Bill . Cohen
[SI-LIST] Re: Reducing SSO noise in an FPGA - Fabrizio Zanella
[SI-LIST] Re: Reducing SSO noise in an FPGA - Chris Cheng
[SI-LIST] Re: Reducing SSO noise in an FPGA - Ken Cantrell
[SI-LIST] Job Opening - Pete Deyring
[SI-LIST] Re: op-amp compensation capacitor in digital cmos process - Bi Han
[SI-LIST] Re: Reducing SSO noise in an FPGA - Charles Grasso
[SI-LIST] Re: Reducing SSO noise in an FPGA - Wyland
[SI-LIST] HyperlynxSI issue - Santhosh E P
[SI-LIST] ibis in hspice - =?big5?b?U3RhbmxleS5DaGl1KKr0q6uyTSk=?=
[SI-LIST] Re: HyperlynxSI issue - Charles Grasso
[SI-LIST] R: ibis in hspice - Guasti Giovanni
[SI-LIST] Re: Reducing SSO noise in an FPGA - Bradley S Henson
[SI-LIST] Re: Reducing SSO noise in an FPGA - Ken Cantrell
[SI-LIST] Re: op-amp compensation capacitor in digital cmos process - Bill . Cohen
[SI-LIST] PCI-Express System Level Trace Impedance Value - Chan, Michael (Eng Hou)
[SI-LIST] Re: Reducing SSO noise in an FPGA - Brown, Mike (AUS)
[SI-LIST] Re: PCI-Express System Level Trace Impedance Value - Coleman, Dave
[SI-LIST] R: PCI-Express System Level Trace Impedance Value - Guasti Giovanni
[SI-LIST] Re: ibis in hspice - Ingraham, Andrew
[SI-LIST] Re: PCI-Express System Level Trace Impedance Value - Dunbar, Tony
[SI-LIST] Microstrip Inductance - Sainath Nimmagadda
[SI-LIST] Re: PCI-Express System Level Trace Impedance Value - Coleman, Dave
[SI-LIST] Re: HyperlynxSI issue - Angulo, John
[SI-LIST] Re: PCI-Express System Level Trace Impedance Value - Coleman, Dave
[SI-LIST] Re: PCI-Express System Level Trace Impedance Value - Chan, Michael (Eng Hou)
[SI-LIST] Re: Reducing SSO noise in an FPGA - Jack Stone
[SI-LIST] Re: Reducing SSO noise in an FPGA - Chris Cheng
[SI-LIST] Re: Reducing SSO noise in an FPGA - Charles Grasso
[SI-LIST] Re: si-list Digest V3 #194 - Thomas Beneken
[SI-LIST] Battery model - JP
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Re: Reducing SSO noise in an FPGA - Lee Ritchey
[SI-LIST] Any good document for DC offset compensation? - Bi Han
[SI-LIST] Re: si-list Digest V3 #194 - andrew . c . byers
[SI-LIST] Re: Reducing SSO noise in an FPGA - Chris Cheng
[SI-LIST] Re: Reducing SSO noise in an FPGA - Mark Alexander
[SI-LIST] Distant Reference Planes Through Other Planes - Brown, William G
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Re: si-list Digest V3 #194 - andrew . c . byers
[SI-LIST] Re: Distant Reference Planes Through Other Planes - Kim Flint
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Re: Distant Reference Planes Through Other Planes - Ege Engin
[SI-LIST] Help! - wgf218
[SI-LIST] spice to ibis - karan bagga
[SI-LIST] Finding Er (Permitivity) - Kamal EC
[SI-LIST] Re: Finding Er (Permitivity) - Clewell, Craig
[SI-LIST] 2.5Gbps - Dorin
[SI-LIST] Re: Finding Er (Permitivity) - Peterson, James F (FL51)
[SI-LIST] Re: Finding Er (Permitivity) - Clewell, Craig
[SI-LIST] Re: 2.5Gbps - Zabinski, Patrick J.
[SI-LIST] Re: Finding Er (Permitivity) - Tim Hochberg
[SI-LIST] Re: Recommendation for high-speed digital inputprotection? - Roman PRAGER
[SI-LIST] Re: Finding Er (Permitivity) - jeff_latourrette
[SI-LIST] Re: Recommendation for high-speed digital input protection? - JMurphy
[SI-LIST] Re: Help! - Harry Selfridge
[SI-LIST] LICA caps? - Fasig, Jonathan L.
[SI-LIST] Re: LICA caps? - Michael Khusid
[SI-LIST] Re: LICA caps? - Istvan Novak - Board Design Technology
[SI-LIST] Re: Finding Er (Permitivity) - V S
[SI-LIST] Re: Finding Er (Permitivity) - Juergen Flamm
[SI-LIST] Re: si-list Digest V3 #194 - art_porter
[SI-LIST] Re: Finding Er (Permitivity) - V S
[SI-LIST] Re: si-list Digest V3 #194 - andrew . c . byers
[SI-LIST] Re: Inductance vs. Impedance - Scott McMorrow
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Re: Inductance vs. Impedance - Vinu Arumugham
[SI-LIST] Re: Inductance vs. Impedance - andrew . c . byers
[SI-LIST] Re: si-list Digest V3 #194 - andrew . c . byers
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Re: Finding Er (Permitivity) - Abe Riazi
[SI-LIST] Re: si-list Digest V3 #194 - Grasso, Charles
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Re: si-list Digest V3 #194 - Wen Fred-Q16099
[SI-LIST] Re: Recommendation for high-speed digital input protection? - Bart Bouma
[SI-LIST] FPGA interface with PS/2 Mouse - Adeel Malik
[SI-LIST] Re: Recommendation for high-speed digital input pro tection? - Geoff Stokes
[SI-LIST] Re: 2.5Gbps - Dorin
[SI-LIST] Re: 2.5Gbps - Paul Levin
[SI-LIST] Tpd Spreadsheet uploaded to si-list web file archives - Ray Anderson
[SI-LIST] Re: 2.5Gbps - Zabinski, Patrick J.
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Behavioral modeling - Panch Chandrasekaran
[SI-LIST] Re: si-list Digest V3 #194 - Michael Smith
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Re: Behavioral modeling - Muranyi, Arpad
[SI-LIST] Re: Behavioral modeling - Panch Chandrasekaran
[SI-LIST] 2.5 D numerical softwares - haowang
[SI-LIST] Re: si-list Digest V3 #194 - john lipsius
[SI-LIST] Re: Behavioral modeling - Muranyi, Arpad
[SI-LIST] More jobs at Sigrity! - Teo Yatman
[SI-LIST] Re: PCB signal speed over temperature - Song, Wil Choon
[SI-LIST] Re: Behavioral modeling - Mirmak, Michael
[SI-LIST] Re: si-list Digest V3 #200 - Thomas Beneken
[SI-LIST] Re: PCB signal speed over temperature - art_porter
[SI-LIST] Re: PCB signal speed over temperature - e.sweetman
[SI-LIST] Re: 2.5 D numerical softwares - Swanson, Dan
[SI-LIST] Re: Tpd Spreadsheet uploaded to si-list web file archives - Ray Anderson
[SI-LIST] AW: Re: PCB signal speed over temperature - mathias . borcke
[SI-LIST] Re: 2.5 D numerical softwares - Jon Powell
[SI-LIST] Re: PCB signal speed over temperature (and findingEr) - Scott McMorrow
[SI-LIST] Resource for Equivlent Circuit Models - Moeller, Merrick
[SI-LIST] Re: si-list Digest V3 #194 - Dr. Howard Johnson
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Capacitor ESR - mappiani
[SI-LIST] Re: Capacitor ESR - Doug Smith
[SI-LIST] Re: Behavioral modeling - Donnelly, Mike
[SI-LIST] Re: Resource for Equivlent Circuit Models - Ray Anderson
[SI-LIST] Re: Resource for Equivlent Circuit Models - Moeller, Merrick
[SI-LIST] Re: Distant Reference Planes Through Other Planes - Brown, William G
[SI-LIST] Re: si-list Digest V3 #194 - john lipsius
[SI-LIST] Re: Behavioral modeling - Jon Powell
[SI-LIST] Re: Behavioral modeling - Muranyi, Arpad
[SI-LIST] Re: Distant Reference Planes Through Other Planes - Salkow, Steven
[SI-LIST] SPICE to IBIS Methodology webinar - Lynne Green
[SI-LIST] Why we need to add input buffer for RF amplifier? - Bi Han
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Cadence Schematic File - Arshad Suhail Farooqui
[SI-LIST] Re: PCB signal speed over temperature (and finding Er) - Song, Wil Choon
[SI-LIST] Re: 2.5 D numerical softwares - Scott McMorrow
[SI-LIST] gnd plane kept close to track - karan bagga
[SI-LIST] Re: Capacitor ESR - Krina Kothari
[SI-LIST] MOS cap on chip for DECOUPLING - Bi Han
[SI-LIST] trace delay/inch - Santhosh E P
[SI-LIST] Re: gnd plane kept close to track - karan bagga
[SI-LIST] Re: MOS cap on chip for DECOUPLING - Rajat Chauhan
[SI-LIST] Re: gnd plane kept close to track - Geoff Stokes
[SI-LIST] Re: gnd plane kept close to track - Geoff Stokes
[SI-LIST] PCI-Express Clarifications. - Rahul R
[SI-LIST] Hi - kirana na
[SI-LIST] Calculate Driver Impedance from IBIS - Miltos Dalakidis
[SI-LIST] Re: Resource for Equivlent Circuit Models - Moeller, Merrick
[SI-LIST] Re: MOS cap on chip for DECOUPLING - Steve Horne
[SI-LIST] Re: MOS cap on chip for DECOUPLING - Steve Horne
[SI-LIST] Re: MOS cap on chip for DECOUPLING - Bill . Cohen
[SI-LIST] Re: gnd plane kept close to track - Loyer, Jeff
[SI-LIST] Please turn off your account when OOP - Loyer, Jeff
[SI-LIST] Re: Please turn off your account when OOP - Matthew Humphreys
[SI-LIST] Re: Please turn off your account when OOP - Doug Smith
[SI-LIST] Re: gnd plane kept close to track - Geoff Stokes
[SI-LIST] Re: Please turn off your account when OOP - ruston, matt
[SI-LIST] Re: gnd plane kept close to track - Loyer, Jeff
[SI-LIST] Re: Please turn off your account when OOP - Michael Poimboeuf
(no subject) - Kirti Barpande
[SI-LIST] Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] Re: Please turn off your account when OOP - Ray Anderson
[SI-LIST] Re: (no subject) - Alfred P. Neves
[SI-LIST] Re: Please turn off your account when OOP - Ray Anderson
[SI-LIST] Reduce the slew rate of a driver - Nelson Rasquinha
[SI-LIST] Re: (no subject) - Paul Levin
[SI-LIST] Re: Reduce the slew rate of a driver - Joel Brown
[SI-LIST] Mentor Hyperlinx ? - Joel Brown
[SI-LIST] Re: Mentor Hyperlinx ? - dan bostan
[SI-LIST] Re: Mentor Hyperlinx ? - Joel Brown
[SI-LIST] Re: 500 MHZ Squarewave (was (no subject)) - Fred Townsend
[SI-LIST] Re: Please turn off your account when OOP - Knighten, Jim L
[SI-LIST] Re: Mentor Hyperlinx ? - Scott McMorrow
[SI-LIST] Re: Mentor Hyperlinx ? - David Kaiser
[SI-LIST] Re: gnd plane kept close to track - Fred U. Rosenberger
[SI-LIST] Re: MOS cap on chip for DECOUPLING - Raymond . Leung
[SI-LIST] how to measure the coupling effect of the coupled lines with vector network analyzer - Liu Ye
[SI-LIST] Re: how to measure the coupling effect of the coupled lineswith vector network analyzer - Paul Levin
[SI-LIST] Re: Mentor Hyperlinx ? - k EPD
[SI-LIST] Re: MOS cap on chip for DECOUPLING - Bi Han
[SI-LIST] Re: how to measure the coupling effect of the coupled lines with vector network analyzer - Bi Han
[SI-LIST] MECL - karan bagga
[SI-LIST] Fwd: Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] 答复: Re: how to measure the coupling effect of the coupled lines with vector network analyzer - ji-wei_du
[SI-LIST] Re: MOS cap on chip for DECOUPLING - Rajat Chauhan
[SI-LIST] Antw: MECL - Robert Nowak
[SI-LIST] Re: how to measure the coupling effect of the coupled lines with vector network analyzer - Guasti Giovanni
[SI-LIST] Re: Mentor HyperLynx ? - Subramanya C K
[SI-LIST] Power planes - karan bagga
[SI-LIST] Re: MECL - Geoff Stokes
[SI-LIST] pl. comment on my stack up - karan bagga
[SI-LIST] Re: Fwd: Re: si-list Digest V3 #194 - SIMSCO_RADT
[SI-LIST] How to calculate output impedance? - Pfeifer, Alan
[SI-LIST] Re: Power planes - Ray Anderson
[SI-LIST] Re: Power planes - Tabatchnick, Justin
[SI-LIST] Re: Power planes - Ray Anderson
[SI-LIST] Re: Power planes - Scott McMorrow
[SI-LIST] Re: Power planes - jeff_latourrette
[SI-LIST] Re: Power planes - Ray Anderson
[SI-LIST] Re: si-list Digest V3 #194 - Dr. Howard Johnson
[SI-LIST] AGTL - Raymond Langlois
[SI-LIST] Re: Power planes - Doug Brooks
[SI-LIST] Re: Power planes - Tabatchnick, Justin
[SI-LIST] Re: AGTL - Prakash Chauhan
[SI-LIST] Re: Fwd: Re: si-list Digest V3 #194 - Sainath Nimmagadda
[SI-LIST] HS Ground and Power ground seperation - Tabatchnick, Justin
[SI-LIST] Re: Mentor Hyperlinx ? - Hargin, Bill
[SI-LIST] A general question of -48V power supply - 宜帆
[SI-LIST] Re: HS Ground and Power ground seperation - christopher . heard
[SI-LIST] Re: A general question of -48V power supply - Nagel, Michael
[SI-LIST] Re: Power planes - Geoff Stokes
[SI-LIST] Cadstar SI & Zuken Hot Stage - Paul Bicknell
[SI-LIST] Re: Cadstar SI & Zuken Hot Stage - Ram Ram Ram
[SI-LIST] SPICE Tools - Moeller, Merrick
[SI-LIST] Crystal modelling parameters and parallel resonance frequency formula - Jean_Pierre . Bouthemy
[SI-LIST] Re: SPICE Tools - Matthias Weingart
[SI-LIST] Spice Tools - Moeller, Merrick
[SI-LIST] Re: A general question of -48V power supply - Robert Friedman
[SI-LIST] PSPICE to HSPICE - Kuan-Wei Wu
[SI-LIST] Re: Crystal modelling parameters and parallel resonance frequency formula - Ray Anderson
[SI-LIST] Re: Spice Tools - Matthias Weingart
[SI-LIST] Re: HS Ground and Power ground seperation - timoceous
[SI-LIST] Re: A general question of -48V power supply - Tom Biggs
[SI-LIST] OOP problem, changing Reply-To header - Matthias Weingart
[SI-LIST] Re: OOP problem, changing Reply-To header - art_porter
[SI-LIST] Conversion from dB to ohm - Bob Patel
[SI-LIST] Re: Conversion from dB to ohm - Larry Barnes
[SI-LIST] Re: Conversion from dB to ohm - Perry Qu
[SI-LIST] Re: Conversion from dB to ohm - Ray Anderson
[SI-LIST] Re: Crystal Oscillator - Ray Anderson
[SI-LIST] CPWG - Bob Patel
[SI-LIST] Re: Crystal Oscillator - pankaj kumar
[SI-LIST] Re: Crystal Oscillator - Ray Anderson
[SI-LIST] pwr/ground - Ted Leyes
[SI-LIST] least inductance path(return current) - karan bagga
[SI-LIST] Re: least inductance path(return current) - Ege Engin
[SI-LIST] Re: least inductance path(return current) - Ingraham, Andrew
[SI-LIST] HSPICE Control options for crystal simulations - Yehuda Yizraeli
[SI-LIST] Presentation on new pcb reference designs and models - Julian Ferry
[SI-LIST] New SI jobs at Sigrity - Teo Yatman
[SI-LIST] ebd to hspice conversion - V S
[SI-LIST] Microstrip Inductance (Old Wine in New Bottle) - Dr. Sainath Nimmagadda
[SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) - Ed Priest
[SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) - Dr. Sainath Nimmagadda
[SI-LIST] Tantalum chip capacitors in CPCI Platform! - Avi Hayun
[SI-LIST] Capacitors and Anti-resonance - Paradis, Daniel
[SI-LIST] Re: Capacitors and Anti-resonance - Istvan Novak - Board Design Technology
[SI-LIST] Losses - 2.5Gbps on FR4 - Dorin
[SI-LIST] Re: Losses - 2.5Gbps on FR4 - Geoff Stokes
[SI-LIST] Re: Losses - 2.5Gbps on FR4 - jeff_latourrette
[SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) - john lipsius
[SI-LIST] Re: Losses - 2.5Gbps on FR4 - Dima Smolyansky
[SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) - Ray Anderson
[SI-LIST] Re: OOP problem, changing Reply-To header - Ray Anderson
[SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) - Dr. Sainath Nimmagadda
[SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) - Ray Anderson
[SI-LIST] Re: Losses - 2.5Gbps on FR4 - Raymond W. Waugh
[SI-LIST] Re: OOP problem, changing Reply-To header - Michael Poimboeuf
[SI-LIST] Re: A general question of -48V power supply - Fred Townsend
[SI-LIST] Re: OOP problem, changing Reply-To header - Loyer, Jeff
[SI-LIST] This is a test OOP - Ray Anderson
[SI-LIST] Anti Vacation Message Grand Experiment - Ray Anderson
[SI-LIST] Re: Anti Vacation Message Grand Experiment - Atul Rastogi
[SI-LIST] Re: Anti Vacation Message Grand Experiment - Ray Anderson
[SI-LIST] Bart Bouma/RMD/PHYCOMP/YAGEO is out of the office. - Bart Bouma
[SI-LIST] Re: OOP problem, changing Reply-To header - Robert Sefton
[SI-LIST] Re: What is OO'P'? - ikanno
[SI-LIST] Re: OOP problem, changing Reply-To header - Paglia, Frank M
[SI-LIST] Re: Capacitors and Anti-resonance - Paradis, Daniel
[SI-LIST] OOPS Test - Girish Bangalore
[SI-LIST] Re: What is OO'P'? - ikanno
[SI-LIST] Re: Losses - 2.5Gbps on FR4 - Scott McMorrow
[SI-LIST] Re: OOP problem, changing Reply-To header - Geoff Stokes
[SI-LIST] SI Job Opening -= Foxconn - Barry Rowland
[SI-LIST] Antw: Re: Capacitors and Anti-resonance - Robert Nowak
[SI-LIST] threshold - hariharan
[SI-LIST] QDRII FPGA design - Chris Betz
[SI-LIST] Re: threshold - Clewell, Craig
[SI-LIST] Re: threshold - Larry Barnes
[SI-LIST] Re: threshold - Bill Reams
[SI-LIST] TDR Transform - Moeller, Merrick
[SI-LIST] Re: threshold - McCoy, Bart O.
[SI-LIST] Re: Losses - 2.5Gbps on FR4 - Perry Qu
[SI-LIST] Re: threshold - Rich Peyton
[SI-LIST] Re: threshold - Robert Szalapski
[SI-LIST] si-list experiment - Ray Anderson
[SI-LIST] Re: threshold - Bill Reams
[SI-LIST] Re: Capacitors and Anti-resonance - Lee Ritchey
[SI-LIST] Autoreply: - Ray Anderson
[SI-LIST] Re: Capacitors and Anti-resonance - Paradis, Daniel
[SI-LIST] Out of Office AutoReply: - Ray Anderson
[SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) - Dr. Sainath Nimmagadda
[SI-LIST] Re: threshold - hansm
[SI-LIST] Re: Capacitors and Anti-resonance - Lee Ritchey
[SI-LIST] High Speed Design Books.. - Rahul R
[SI-LIST] Re: High Speed Design Books.. - Hossain, Mohammed M
[SI-LIST] Re: High Speed Design Books.. - Alex Slavec
[SI-LIST] Re: High Speed Design Books.. - Fred Balistreri
[SI-LIST] Re: High Speed Design Books.. - Andy Kuo
[SI-LIST] More High Speed Design Books - mmunroe
[SI-LIST] Re: More High Speed Design Books - duane takahashi
[SI-LIST] Re: CPWG - D G
[SI-LIST] Re: TDR Transform - D G
[SI-LIST] Quasi Static Assumptions - Moeller, Merrick
[SI-LIST] Re: TDR Transform - Moeller, Merrick
[SI-LIST] Re: PCI-Express Clarifications. - Option juggler
[SI-LIST] Re: Quasi Static Assumptions - Hassan O. Ali
[SI-LIST] Re: Quasi Static Assumptions - Hassan O. Ali
[SI-LIST] UltraCAD ESR and Bypass Capacitor Caculator - Abe Riazi
[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator - Abe Riazi
[SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) - Dr. Sainath Nimmagadda
[SI-LIST] IBIS packaging models - Russell Rapport
[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator - Zelno, John
[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator - Paul Levin
[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator - Lee Ritchey
[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator - john lipsius
[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator - john lipsius
[SI-LIST] Re: Quasi Static Assumptions - McCoy, Bart O.
[SI-LIST] Re: threshold - Jacobson, Karl
[SI-LIST] Re: threshold and 60 Hz - Wyland
[SI-LIST] how to start high speed PCB design ? - zhou lin