[SI-LIST] Re: Reducing SSO noise in an FPGA

Ken,
The duration was very short about 0.5nS (if memory
serves). Typically the pulse is a peak right at the
cross over point mid way between the output
is turning off (or on).

The external capacitance was a trace and RAM load.

chas

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ken Cantrell
Sent: Wednesday, July 16, 2003 7:15 AM
To: Charles Grasso; chris.cheng@xxxxxxxxxxxx; 'Fabrizio Zanella'
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA


Chuck,
I've never measured it, so I couldn't tell you for sure.  > 40 ma for a 5 ma
(constant current source?) driver sounds like a lot.  On the surface, it
seems like the driver would burn up.  What was the duration of the event?
How much external capacative loading were you using?
Ken

-----Original Message-----
From: Charles Grasso [mailto:cgrassosprint1@xxxxxxxxxxxxx]
Sent: Tuesday, July 15, 2003 11:13 PM
To: Ken.Cantrell@xxxxxxxxxxx; chris.cheng@xxxxxxxxxxxx; 'Fabrizio
Zanella'
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA


Hi Ken - I have a Q on this.

I have done simulations on BGAs and looked at the
current waveforms that the sims predict. Instead of the
*wimpy* 5mA or so that the manf puts in the data
sheets, I am observing >40mA at the switching
transitions. I put this down to primarily the
momentary short that exists as the device chages state.
Have you (or others) similar experiences or are the
data sheets accurate?

Incidentally as an EMI guy the >40mA is extremely
interesting to me..!!

Charles Grasso


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ken Cantrell
Sent: Tuesday, July 15, 2003 1:21 PM
To: chris.cheng@xxxxxxxxxxxx; 'Fabrizio Zanella'
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA


Or go to a class 1 if you are using a class 2 (7.2 mA vs 15.7 ma)

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
Sent: Tuesday, July 15, 2003 2:09 PM
To: 'Fabrizio Zanella'; Chris Cheng
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA


Sure you can, don't you have an external series resistor and parallel
terminator you can play around their values ?

-----Original Message-----
From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
Sent: Tuesday, July 15, 2003 12:58 PM
To: chris.cheng@xxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA


I cannot reduce the drive strength, the drivers are SSTL2.  We reduced
the SSO noise significantly by turning off half the data bits.

-----Original Message-----
From: Chris Cheng [mailto:chris.cheng@xxxxxxxxxxxx]
Sent: Tuesday, July 15, 2003 2:27 PM
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA

What's wrong with reducing the driving strength of the drivers in the
FPGA ?
Are you at the limit of the lowest possible drive strength already ?

-----Original Message-----
From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
Sent: Tuesday, July 15, 2003 5:54 AM
To: bhenson@xxxxxxxxxxxx; Ken.Cantrell@xxxxxxxxxxx
Cc: bill.panos@xxxxxxxxxxxxxxx; Chris Cheng; scott@xxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA


This discussion has turned quite interesting.  There have been several
comments which imply that the only way to reduce SSO noise in an
FPGA/ASIC is to add decoupling at the die or inside the package.  These
are fixes which only the device manufacturers can make.
Does anyone have measurement/simulation data on what effect adding many
decoupling capacitors under the BGA package, between VCC and ground
balls, will have on the SSO noise?

Thanks and regards,
Fabrizio

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