Posts for si-list, 06-2003

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» [SI-LIST] Re: how to model an oscillator ? -
» [SI-LIST] how to model an oscillator ? -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] cmic champion memory controller -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] I/O standard flexibility -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: via ? -
» [SI-LIST] Re: Reducing SSO noise in an FPGA] -
» [SI-LIST] Re: via ? -
» [SI-LIST] Re: Paper: Understanding the Importance of Signal Integrity -
» [SI-LIST] Re: via ? -
» [SI-LIST] Re: via ? -
» [SI-LIST] Re: via ? -
» [SI-LIST] Re: Reducing SSO noise in an FPGA] -
» [SI-LIST] via ? -
» [SI-LIST] Re: Paper: Understanding the Importance of Signal Integrity -
» [SI-LIST] Re: Paper: Understanding the Importance of Signal Integrity -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Paper: Understanding the Importance of Signal Integrity -
» [SI-LIST] Paper: Understanding the Importance of Signal Integrity -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Current Return Path -
» [SI-LIST] Re: Current Return Path -
» [SI-LIST] Re: Current Return Path -
» [SI-LIST] Re: Current Return Path -
» [SI-LIST] Re: Current Return Path -
» [SI-LIST] Current Return Path -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA _ Capacitor ESL-values -
» [SI-LIST] Comaprison of hotstage(zuken) and hyperlynx -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Flash with JTAG ISP -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: VIA Capacity--> This Program was designed by Ph illi p Restall -->Via_Current_spreadsheet_phillip_restall.xls -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Eye display -
» [SI-LIST] Re: Eye display -
» [SI-LIST] Re: Eye display -
» [SI-LIST] Re: Eye display -
» [SI-LIST] Eye display -
» [SI-LIST] Reducing SSO noise in an FPGA -
» [SI-LIST] RMCEMC June meeting available for download -
» [SI-LIST] Question on chassis ground -
» [SI-LIST] Re: Damped voltage oscillation -
» [SI-LIST] Re: VNA Calibration -
» [SI-LIST] Re: VIA Capacity--> This Program was designed by Philli p Restall -
» [SI-LIST] Re: How to generate unloaded driver waveform -
» [SI-LIST] Re: PCI input setup time question -
» [SI-LIST] PCI input setup time question -
» [SI-LIST] Re: How to generate unloaded driver waveform (error correction) -
» [SI-LIST] Re: How to generate unloaded driver waveform -
» [SI-LIST] How to generate unloaded driver waveform -
» [SI-LIST] Re: VNA Calibration -
» [SI-LIST] Re: Damped voltage oscillation -
» [SI-LIST] Re: VIA Capacity -
» [SI-LIST] Re: gtl signal ? -
» [SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDDdroop & Ground Bounce -
» [SI-LIST] Re: VIA Capacity -
» [SI-LIST] Re: VIA Capacity -
» [SI-LIST] VIA Capacity -
» [SI-LIST] High Speed SoC Bus -
» [SI-LIST] Re: Trace coating! -
» [SI-LIST] Re: Damped voltage oscillation -
» [SI-LIST] Re: Five emerging technologies that will revolutionize high speed systems presentation at HCA mtg -
» [SI-LIST] Re: Damped voltage oscillation -
» [SI-LIST] Re: Damped voltage oscillation -
» [SI-LIST] Re: Damped voltage oscillation -
» [SI-LIST] Re: Damped voltage oscillation -
» [SI-LIST] Damped voltage oscillation -
» [SI-LIST] Trace coating! -
» [SI-LIST] VISIT MY WEBSITE:http://www.geocities.com/ghori60/ghori.html -
» [SI-LIST] query. -
» [SI-LIST] Place and Route!!! -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Effective Inductance -
» [SI-LIST] Five emerging technologies that will revolutionize high speed systemspresentation at HCA mtg -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Re: VNA/VSA question -
» [SI-LIST] VNA/VSA question -
» [SI-LIST] Re: VNA Calibration -
» [SI-LIST] VNA Calibration -
» [SI-LIST] si-list Digest V3 #171 -
» [SI-LIST] On-die decoupling MOS capacitor -
» [SI-LIST] AGP testing load -
» [SI-LIST] Re: On-die decoupling MOS capacitor -
» [SI-LIST] On-die decoupling MOS capacitor -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Inductance extraction with FastHenry -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Re: Presentations @ DesignCon EAST -
» [SI-LIST] Presentations @ DesignCon EAST -
» [SI-LIST] Re: Reference plane -
» [SI-LIST] signal integrity seminar - June 26 -27, 2003 -
» [SI-LIST] Re: Orcad layout to Allegro -
» [SI-LIST] srec2flash utility -
» [SI-LIST] Reference plane -
» [SI-LIST] How to fill copper? -
» [SI-LIST] Re: Orcad layout to Allegro -
» [SI-LIST] Orcad layout to Allegro -
» [SI-LIST] clock tree at GHz range -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Re: Developing High Speed Routing Rules -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] High Speed Soc Busses -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] Re: pcb stackup -
» [SI-LIST] pcb stackup -
» [SI-LIST] Re: s2ibis -
» [SI-LIST] PCB signal speed over temperature -
» [SI-LIST] Issues WITH HPI Bus b/w ARM and TI DSP -
» [SI-LIST] Re: Developing High Speed Routing Rules -
» [SI-LIST] Re: Developing High Speed Routing Rules -
» [SI-LIST] Re: Developing High Speed Routing Rules -
» [SI-LIST] Re: Developing High Speed Routing Rules -
» [SI-LIST] Developing High Speed Routing Rules -
» [SI-LIST] Re: Image Conscious? -
» [SI-LIST] Re: Image Conscious? -
» [SI-LIST] Image Conscious? -
» [SI-LIST] RMCEMC June 20th meeting reminder -
» [SI-LIST] Sigrity seeks Regional Sales Account Manager -
» [SI-LIST] ESD Calibration procedure -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: Looking for Job -
» [SI-LIST] Looking for Job -
» [SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce -
» [SI-LIST] s2ibis -
» [SI-LIST] Transient Analysis in Spectre -
» [SI-LIST] Agenda, IBIS Open Forum Summit at DesignCon East -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce -
» [SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: PCI Bus Routing -
» [SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce -
» [SI-LIST] Re: PCI Bus Routing -
» [SI-LIST] Job Opportunities at Optimal Corporation -
» [SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce -
» [SI-LIST] FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce -
» [SI-LIST] Re: Hspice simulator for board designs -
» [SI-LIST] Re: JOIN FOR FREE! LEARN and EARN! -
» [SI-LIST] Fw: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce -
» [SI-LIST] JOIN FOR FREE! LEARN and EARN! -
» [SI-LIST] Re: Virus Attachments? -
» [SI-LIST] Re: More on Viruses -
» [SI-LIST] Re: Virus Attachments? -
» [SI-LIST] Re: Virus Attachments? -
» [SI-LIST] More on Viruses -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Virus Attachments? -
» [SI-LIST] Re: More On Viruses -
» [SI-LIST] Re: Virus Attachments? -
» [SI-LIST] Re: More On Viruses -
» [SI-LIST] More On Viruses -
» [SI-LIST] Virus Attachments? -
» [SI-LIST] Re: How do we choose the proper test load? -
» [SI-LIST] How do we choose the proper test load? -
» [SI-LIST] Re: SPECCTRAQuest vs. HyperLynx -
» [SI-LIST] Re: Crystal Oscillator Overtones. -
» [SI-LIST] Re: SPECCTRAQuest vs. HyperLynx -
» [SI-LIST] Re: SPECCTRAQuest vs. HyperLynx -
» [SI-LIST] SPECCTRAQuest vs. HyperLynx -
» [SI-LIST] Re: Overshoot and Undershoot Measurement Specification Question -
» [SI-LIST] Re: Standard Interfacing techniques fo quartzr crystal oscillators -
» [SI-LIST] Standard Interfacing techniques fo quartzr crystal oscillators -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: Hspice simulator for board designs -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Importing Device pad netlists and design kits spice models into ADS -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Overshoot and Undershoot Measurement Specification Question -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Hspice simulator for board designs -
» [SI-LIST] Re: PCI 4.3.6.2. System Board Impedance -
» [SI-LIST] Re: Hspice simulator for board designs -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] PCI 4.3.6.2. System Board Impedance -
» [SI-LIST] PCI Question -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: Hspice simulator for board designs -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Hspice simulator for board designs -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Hspice simulator for board designs -
» [SI-LIST] Re: [RE]Impulse response of MMF - implementing FO models in SPICE -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] Re: delay vs. transmission line length -
» [SI-LIST] delay vs. transmission line length -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductanc e -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: IBIS Timing Analysis -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: IBIS Timing Analysis -
» [SI-LIST] Re: IBIS Timing Analysis -
» [SI-LIST] IBIS Timing Analysis -
» [SI-LIST] Re: broadside coupled striplines -
» [SI-LIST] broadside coupled striplines -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: hspice ploting (print) time limits -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: hspice ploting (print) time limits -
» [SI-LIST] Re: hspice ploting (print) time limits -
» [SI-LIST] hspice ploting (print) time limits -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Re: Report Creators -
» [SI-LIST] Report Creators -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] [RE]Impulse response of MMF -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] POSSIBLE VIRUS ALERT: RE: Re: Power supply noise -
» [SI-LIST] POSSIBLE VIRUS ALERT: RE: Re: Power supply noise -
» [SI-LIST] Hspice: Flicker Noise of MOS -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Embedded Systems Developers User Group -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: Common Mode and Differential Termination -
» [SI-LIST] FW: HCA MEETING REMINDER - June 5, 2003 -
» [SI-LIST] Networking help for PCB Designer -
» [SI-LIST] RMCEMC presentation downloads and meeting announcement. -
» [SI-LIST] More inexpensive test equipment -
» [SI-LIST] Re: About the Cref in IBIS Model -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: Caps of plane pairs -
» [SI-LIST] Antw: searching for board-to-board connector withhigh vibration and shock resistance -
» [SI-LIST] searching for board-to-board connector with high vibration and shock resistance -
» [SI-LIST] Re: gtl signal -
» [SI-LIST] gtl signal -
» [SI-LIST] Re: About the Cref in IBIS Model -
» [SI-LIST] About the Cref in IBIS Model -
» [SI-LIST] Re: PCI Bus Routing -
» [SI-LIST] Re: Mixed signal: partitioning GND or unique plane ? -
» [SI-LIST] Re: Crystal Oscillator Overtones. -
» [SI-LIST] Fluorosilicone -
» [SI-LIST] Re: Effective dielectric constant -
» [SI-LIST] Re: Flash with JTAG ISP -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: resend - Specctraquest model: mounted inductance -
» [SI-LIST] Re: Caps of plane pairs -
» [SI-LIST] Flash with JTAG ISP -
» [SI-LIST] Re: gtl signal ? -
» [SI-LIST] Caps of plane pairs -
» [SI-LIST] Flash with JTAG ISP -
» [SI-LIST] Common Mode and Differential Termination -
» [SI-LIST] Re: VNA Question -
» [SI-LIST] resend - Specctraquest model: mounted inductance -
» [SI-LIST] gtl signal ? -
» [SI-LIST] Re: PCI Bus Routing -
» [SI-LIST] Effective dielectric constant -
» [SI-LIST] Re: [Ethernet models and simulation] -
» [SI-LIST] Re: (No Date: Mon, 2 Jun 2003 08:35:29 -0400 -
» [SI-LIST] Re: VNA Question -
» [SI-LIST] VNA Question -