# [SI-LIST] Re: Reducing SSO noise in an FPGA

• From: "Salkow, Steven" <steven.salkow@xxxxxxxx>
• To: "'Michael_Poimboeuf@xxxxxxxxxxxxxx'" <Michael_Poimboeuf@xxxxxxxxxxxxxx>,si-list@xxxxxxxxxxxxx
• Date: Wed, 25 Jun 2003 17:55:20 -0700
```Mr Zhangkun is quite right to suggest that for 100 Mhz no practical =
parts
are known to exist for 0.1uF and 0.22uF that have an effective =
impedance at
100 Mhz. Michael Poimboeuf is right to suggest that low inductance low =
ESR
parts make a difference. Here are a few vendors that have some better =
parts
(higher Q)

For practical parts look at=20

JDI Low Inductance Capacitors at http://www.johansondielectrics.com
AVX http://www.avxcorp.com/docs/masterpubs/lica.pdf
and Syfer Technology http://www.syfer.com/5115.htm
The last vendor states" Correspondingly, an inductance of 1200pH for =
0805
(capacitor) is reduced to around 600pH for the 0508. "

AVX has what they refer to as a LICA=AE (Low Inductance Decoupling =
Capacitor
Arrays)

Small Ceramic capacitor now available up to 15 UF now have better
performance at lower frequencies that previous units.

Steven Salkow
Lockheed Martin
3200 Zanker Rd
San Jose, CA 95134
(408) 473-4058
steven.salkow@xxxxxxxx
Fax (408) 473-3044

> -----Original Message-----
> From: Michael Poimboeuf [SMTP:Michael_Poimboeuf@xxxxxxxxxxxxxx]
> Sent: Wednesday, June 25, 2003 5:27 PM
> To:   si-list@xxxxxxxxxxxxx
> Subject:      [SI-LIST] Re: Reducing SSO noise in an FPGA
>=20
> One shouldn't make a blanket statement that a cap larger than a =
certain =3D
> capacitance is too large for decoupling, you have to consider the =3D
> inductance and the ESR. A low inductance package can push the self =
=3D
> resonance out (proportional to 1/sqrt(LC)) and low ESR can give you =
good =3D
> performance in the region of the self resonant frequency.
>=20
> Paraphrasing Howard Johnson from his book "High Speed Digital =
Design":
> Figure out the package size, which fixes the inductance,
> then use the largest capacitance you can get into that package.
>=20
> Read the book for the fine argument that Dr. Johnson makes... or =
maybe =3D
> he'll chime in here.
>=20
> One caveat is that if you really do need filtering at a specific =3D
> frequency above the self resonance of local (say Y5V) decoupling caps =
=3D
> you can use C0G/NP0 low ESR caps to filter those high frequencies. I =
=3D
> find 2700pF C0G caps give me excellent decoupling for ECL and RF =3D
> circuits.
>=20
> ---
> mkp=3D20
>=20
> -----Original Message-----
> From: Zhangkun [mailto:zhang_kun@xxxxxxxxxx]
> Sent: Wednesday, June 25, 2003 5:04 PM
> To: fzanella@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
>=20
>=20
> Dear Zanella
>=20
> I think 0.1uF and 0.22uF is too large for decoupling. When the =
frequency =3D
> goes up to 100MHz, these two kind of caps will be of no use...
>=20
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```