[SI-LIST] Re: Reducing SSO noise in an FPGA
- From: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>
- To: "'fzanella@xxxxxxxxxxxx'" <fzanella@xxxxxxxxxxxx>,"'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 25 Jun 2003 12:29:54 -0600
Hi Fabrizio,
Very good question and one that has been on my mind
for quite a while for two reasons. One is how on earth
does one even measure SSN/PowerGnd bounce in a
BGA when all the pins are not accessible?
(I have used the paper clip probe - thanks Doug-
and it's a very useful indicator but by no means
definitive, perhaps Doug can expand on this).
The other concern is the seeming incompatibility of the
BGA package with low noise margins. For example typically
for 1.2V logic we use, we look for a 5% noise margin.
Using Larry Smiths power distribution formula, the implication
is we need a 60milliohm max impedance for the *entire*
voltage distribution not just the BGA. 60millihoms
translates to about 20pH of inductance at 500MHz.
Even if you pick the optimal values, I think the
inductance will still dominate.
Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx
-----Original Message-----
From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
Sent: Wednesday, June 25, 2003 10:02 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Reducing SSO noise in an FPGA
I would like to hear about experiences regarding methods of reducing
simultaneous switching noise in a large FPGA, BGA package. Let's assume a
128bit bus, with a signal frequency of 100MHz. How effective is adding
ground planes 2 mils from the VCC planes in reducing SSN? If one uses BC,
does every VCC pin in the FPGA require decoupling? And should the caps be
tied to the BGA pins with blind vias so they can be placed directly under
the BGA? What are the optimal values for the decoupling capacitors, 0.1uf,
0.22uF?
Thanks very much and regards,
Fabrizio Zanella
Principal Hardware Design Engineer
Broadbus Technologies
fzanella@xxxxxxxxxxxx
=20
--------------------------------------------------------
=20
This email message and any files transmitted with it contain = confidential
information intended only for the person(s) to whom this = email message is
addressed. If you have received this email message in = error, please
notify the sender immediately by telephone or email and = destroy the
original message without making a copy. Thank you.=20 =20
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
