[SI-LIST] Re: Reducing SSO noise in an FPGA
- From: "Fabrizio Zanella" <fzanella@xxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 27 Jun 2003 09:34:26 -0400
Thank you for the excellent comments and suggestions by several people.
Here are replies to some of the comments.
- We cannot change the I/O driver slew rate, they're SSTL2.
- The FPGA via holes are at 10 mils, so this is already the smallest
possible for manufacturing. I will look into reducing the antipad size
to increase copper. =20
- Does it make sense to increase the via hole size for the power pins?
- We measured the SSO noise on a bit held high while the 128 SSTL2 bits
were switching, at the BGA balls.
- Does anyone have suggestions for simulating this SSO behavior? I have
access to the FPGA IO spice models, I need to request a good package
model. Any luck out there in simulating SSO using Hspice, or is the
recommendation to use one of the Power Noise tools (Cadence, Sigrity)?
Thanks and regards, Fabrizio
-----Original Message-----
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]=20
Sent: Thursday, June 26, 2003 6:21 PM
To: Fabrizio Zanella
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Reducing SSO noise in an FPGA
Fabrizio,
By now, you've heard many interesting comments, some of which are very=20
good, but none of which gives the entire picture.
The SSN problem can be divided to the following parts that I can think=20
of off the top of my head:
1) Power delivery to the I/O drivers.
2) Signal mode conversion at the die/package substrate boundary.
3) Signal mode conversion at the package/board boundary.
4) Device output impedance matching.
5) Package forward and reverse crosstalk.
6) Board decoupling.
7) Power/ground plane perforation due to antipads.
1) Anything that reduces loop inductance from the die, through the=20
package and to the PCB planes, reduces the SSN effects on power=20
delivery. Select your packages with good I/O power rail and ground=20
ballout patterns.
2) You can't do a darn thing about this, since the FPGA manufacturer=20
takes control of this part of the design. However, how the die is=20
escaped to the package, and which power planes the signals are routed=20
adjacent to, has a huge impact on SSN. If you have a choice, spread=20
your output signals across a wide area of the package, rather than a=20
narrow area or section, as this will distribute the signaling currents=20
across the package.
3) Match the planes that your signals are referenced to to the same=20
reference planes that are used in the package. You'll have to query the
manufacturer regarding this, and you may not obtain the data,=20
unfortunately. By matching planes, you will keep a continuous return=20
path as the signals exits the package and enters your board. You will=20
reduce your noise greatly by doing this. In addition, since there is=20
normally a ground and a power rail supplying current to the I/O driver,=20
You would optimally like to place a power ground plane pair next to=20
your signal layers to provide the best high frequency decoupling and=20
mode conversion control.
4) Select the slowest driver output and whenever possible impedance=20
match the driver to the board trace impedance. Better yet, match the=20
driver to the package trace impedance, and match the trace impedance of=20
the board to your package.. A matched driver will terminate any=20
crosstalk from neighbor lines and reduce the impact of reflected reverse
crosstalk in the package. If your drivers are low impedance and the=20
package is poorly designed (not uncommon in the FPGA world) and if the=20
driver edge rate is extremely fast, reverse crosstalk from adjacent=20
lines can reach total saturation within the package, reflect off the=20
driver, and become launched onto the external. system traces. In fact,=20
for fast edges and poorly designed packages with higher crosstalk=20
coeffieients than the PCB trace, it is entirely possible for stripline=20
traces to build up maximum crosstalk before the signal ever reaches the=20
board. In this case, all your good work at controlling PCB level=20
coupling is all for naught.
5) See #4 ... if you have a choice, have the data available from the=20
manufacturer, or can measure it yourself, choose the package with the=20
lowest crosstalk.
6) Your decoupling capacitors will have an impact on noise reduction at=20
the fundamental switching frequency of the bus, but they are not close=20
enough to impact the SSN due to 128 simultaneous drivers switching.=20
Your decoupling capacitors, due to the time delay between the die and=20
the capacitors, will only have an impact on the long term average noise.
So, use your capacitors to decouple the planes. Follow the breakout=20
recommendations of the many guys from Sun who have given us all such=20
wonderful theoretical and practical work and advice on decoupling. You=20
can make the noise worse by not following their guidelines and advise,=20
but you will not solve problems inherent to SSN within a package.
7) Use the smallest antipad size that you can get away with to reduce=20
the amount of plane perforation. Push your manufacturing process to use
the absolute minimum size via hole, pad and antipad for signal vias.
Finally, if you are designing your own custom bus, rather than=20
interfacing to an existing bus, then roll-your-own balanced coding=20
scheme to limit the number simultaneous signal transitions on the bus.
best regards,
scott
--=20
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
Fabrizio Zanella wrote:
>I would like to hear about experiences regarding methods of reducing
>simultaneous switching noise in a large FPGA, BGA package. Let's
assume
>a 128bit bus, with a signal frequency of 100MHz.
>How effective is adding ground planes 2 mils from the VCC planes in
>reducing SSN? If one uses BC, does every VCC pin in the FPGA require
>decoupling? And should the caps be tied to the BGA pins with blind vias
>so they can be placed directly under the BGA? What are the optimal
>values for the decoupling capacitors, 0.1uf, 0.22uF?
>
>Thanks very much and regards,
>
>
>Fabrizio Zanella
>Principal Hardware Design Engineer
>Broadbus Technologies
>fzanella@xxxxxxxxxxxx
>=3D20
> =20
>
=20
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