It depends how Salkov defines "effective impedance" Here's what I mean. Values below are from AVX website graphs. Look at an 0.1uF AVX X7R for instance in an 0805 package. The SRF is just shy of 20MHz. At 100MHz this give you=20 an effective Z of about .5ohms. Now look at the same dielectric in the same package in a 1000pF value. SRF is around 150MHz and effective Z at 100MHz is about 2ohms =3D> 12dB worse than the 0.1uF cap at 100MHz and 40dB worse at low frequency. Or you could pick a value in between in the same package with the same dielectric, say 0.01uF. The SRF is around 60MHz and the effective Z at 100MHz is 0.5ohms. Same as the 0.1uF at 100MHz but 20dB worse at low frequency. Generally you'll have the same result for the same inductance/SRF and dielectric. Dr. Johnson is right. Biggest cap you can fit in the package. Conventional wisdom of choosing your SRF to be higher than the frequency of interest given the package and dielectric are the same is just plain wrong. The only way it works is if the dielectric has much lower ESR. Substitute C0G material for the parts above (2700pF being the largest cost effective part - but larger values are available at higher cost) and tune to the SRF of the cap to the frequency of interest and you can realize 10dB better attenuation at the frequencies of interest. I make this argument with such vigor because I used to subscribe to the conventional wisdom of .1/.01/.001 three decade decoupling with the same package geometry and dielectric. I was proven wrong. Now I'm right. --- mkp=20 -----Original Message----- From: Salkow, Steven [mailto:steven.salkow@xxxxxxxx] Sent: Wednesday, June 25, 2003 5:55 PM To: Michael Poimboeuf; si-list@xxxxxxxxxxxxx Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA Mr Zhangkun is quite right to suggest that for 100 Mhz no practical = parts are known to exist for 0.1uF and 0.22uF that have an effective impedance = at 100 Mhz. Michael Poimboeuf is right to suggest that low inductance low = ESR parts make a difference. Here are a few vendors that have some better = parts (higher Q) For practical parts look at=20 JDI Low Inductance Capacitors at http://www.johansondielectrics.com AVX http://www.avxcorp.com/docs/masterpubs/lica.pdf and Syfer Technology http://www.syfer.com/5115.htm The last vendor states" Correspondingly, an inductance of 1200pH for = 0805 (capacitor) is reduced to around 600pH for the 0508. " AVX has what they refer to as a LICA=AE (Low Inductance Decoupling = Capacitor Arrays) Small Ceramic capacitor now available up to 15 UF now have better performance at lower frequencies that previous units. Steven Salkow Lockheed Martin 3200 Zanker Rd San Jose, CA 95134 (408) 473-4058 steven.salkow@xxxxxxxx Fax (408) 473-3044 > -----Original Message----- > From: Michael Poimboeuf [SMTP:Michael_Poimboeuf@xxxxxxxxxxxxxx] > Sent: Wednesday, June 25, 2003 5:27 PM > To: si-list@xxxxxxxxxxxxx > Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA >=20 > One shouldn't make a blanket statement that a cap larger than a = certain =3D > capacitance is too large for decoupling, you have to consider the =3D > inductance and the ESR. A low inductance package can push the self =3D > resonance out (proportional to 1/sqrt(LC)) and low ESR can give you = good =3D > performance in the region of the self resonant frequency. >=20 > Paraphrasing Howard Johnson from his book "High Speed Digital Design": > Figure out the package size, which fixes the inductance, > then use the largest capacitance you can get into that package. >=20 > Read the book for the fine argument that Dr. Johnson makes... or maybe = =3D > he'll chime in here. >=20 > One caveat is that if you really do need filtering at a specific =3D > frequency above the self resonance of local (say Y5V) decoupling caps = =3D > you can use C0G/NP0 low ESR caps to filter those high frequencies. I = =3D > find 2700pF C0G caps give me excellent decoupling for ECL and RF =3D > circuits. >=20 > --- > mkp=3D20 >=20 > -----Original Message----- > From: Zhangkun [mailto:zhang_kun@xxxxxxxxxx] > Sent: Wednesday, June 25, 2003 5:04 PM > To: fzanella@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx > Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA >=20 >=20 > Dear Zanella >=20 > I think 0.1uF and 0.22uF is too large for decoupling. When the = frequency =3D > goes up to 100MHz, these two kind of caps will be of no use... >=20 > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >=20 > or to administer your membership from a web page, go to: > http://www.freelists.org/webpage/si-list >=20 > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >=20 > List archives are viewable at: =20 > http://www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages=20 > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: http://www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu