[SI-LIST] Re: Reducing SSO noise in an FPGA

This may or may not be an option for you considering you are running at=
 100MHz, but...
We had a similar problem on a large FPGA with wide buses. Since the SSO=
 noise seemed to be related to the package and not the board, the only=
 option we could see was to change the I/O drivers to slow down the edge=
 rates on the output drivers of those wide buses. It worked beautifully.

David Kaiser
4 McDATA Pkwy.
Broomfield, CO 80021
(720) 558-4431
david.kaiser@xxxxxxxxxx


-----Original Message-----
From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
Sent: Wednesday, June 25, 2003 10:02 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Reducing SSO noise in an FPGA


I would like to hear about experiences regarding methods of reducing
simultaneous switching noise in a large FPGA, BGA package.  Let's assume
a 128bit bus, with a signal frequency of 100MHz.
How effective is adding ground planes 2 mils from the VCC planes in
reducing SSN? If one uses BC, does every VCC pin in the FPGA require
decoupling? And should the caps be tied to the BGA pins with blind vias
so they can be placed directly under the BGA?  What are the optimal
values for the decoupling capacitors, 0.1uf, 0.22uF?

Thanks very much and regards,


Fabrizio Zanella
Principal Hardware Design Engineer
Broadbus Technologies
fzanella@xxxxxxxxxxxx
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