[SI-LIST] Re: Reducing SSO noise in an FPGA
- From: Zhangkun <zhang_kun@xxxxxxxxxx>
- To: fzanella@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 26 Jun 2003 08:03:30 +0800
Dear Zanella
I think 0.1uF and 0.22uF is too large for decoupling. When the frequency goes
up to 100MHz, these two kind of caps will be of no use. Istvan has writen one
paper about measuring caps.
Best Regards
Zhangkun
2003.06.26
----- Original Message -----
From: "Fabrizio Zanella" <fzanella@xxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, June 26, 2003 12:01 AM
Subject: [SI-LIST] Reducing SSO noise in an FPGA
> I would like to hear about experiences regarding methods of reducing
> simultaneous switching noise in a large FPGA, BGA package. Let's assume
> a 128bit bus, with a signal frequency of 100MHz.
> How effective is adding ground planes 2 mils from the VCC planes in
> reducing SSN? If one uses BC, does every VCC pin in the FPGA require
> decoupling? And should the caps be tied to the BGA pins with blind vias
> so they can be placed directly under the BGA? What are the optimal
> values for the decoupling capacitors, 0.1uf, 0.22uF?
>
> Thanks very much and regards,
>
>
> Fabrizio Zanella
> Principal Hardware Design Engineer
> Broadbus Technologies
> fzanella@xxxxxxxxxxxx
> =20
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