Scott, Did hell freezes over :-D ? Did I hear SPICE ? Actually, the most important part is a good SPICE driver model and the right program to drive patterns into the bus. Measure a bit stuck at high or low while the rest are switching hi/low together. Adjust the inductance of the I/O power/gnd on your model until the SSO bounce observed at the pin in simulation matches what you measured. Scale it with the signal to pwr/gnd ratio and you get yourself a basic first order SSO model. The beauty of this is you don't even have to know anything about the package (well, at least if the package design is done correctly). To achieve the desire SSO level, change the value of the inductance until you reach the level need. The ratio between the actual inductance measre vs. the inductance need to be acceptable is the number of excess pwr/gnd pins (extra+current) needed vs. your current pwr/gnd pins. Or you can add dummy signals that won't switch to take advantage of the I/O pwr/gnd pins in that block. That's as much as you can do on a FPGA short of changing the protocol of the bus or the termination scheme. I still don't understand all these talks about quality of bypass cap on PCB or 2 mil pwr/gnd planes on PCB. They have little or nothing to do with managing SSO (which is a return current problem between the signal and pwr/gnd). You are better off managing your reference planes to your signals than any bypass cap you can put on your PCB (which I think is useless for solving SSO problem). BTW, good summary on your first response. That should be put in a SI-list FAQ. Chris -----Original Message----- From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx] Sent: Friday, June 27, 2003 7:52 AM To: silist Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA Yes, you can simulate these effects with Hspice, but you need to have extremely good package model extracts, which are hardly ever done. Sigrity is a good way to go, however, any simulation with 128 I/O cells will be extremely difficult to do and time consuming. For a Sigrity type simulation, you will need to have access to the entire package layout, all stackup and materials information, and will need to use a very small mesh size, in order to capture all the effects between all the via scattering in the package. I doubt, however, that you will obtain much useful information from your FPGA vendor on the true characteristics of the package. If you do, you will be extremely lucky. We've made these sorts of simulations and studies before, but it was as part of consultation we delivered to FPGA and ASIC semiconductor vendors. regards, scott -- Scott McMorrow Teraspeed Consulting Group LLC 2926 SE Yamhill St. Portland, OR 97214 (503) 239-5536 http://www.teraspeed.com Fabrizio Zanella wrote: >Thank you for the excellent comments and suggestions by several people. >Here are replies to some of the comments. >- We cannot change the I/O driver slew rate, they're SSTL2. >- The FPGA via holes are at 10 mils, so this is already the smallest >possible for manufacturing. I will look into reducing the antipad size >to increase copper. =20 >- Does it make sense to increase the via hole size for the power pins? >- We measured the SSO noise on a bit held high while the 128 SSTL2 bits >were switching, at the BGA balls. >- Does anyone have suggestions for simulating this SSO behavior? I have >access to the FPGA IO spice models, I need to request a good package >model. Any luck out there in simulating SSO using Hspice, or is the >recommendation to use one of the Power Noise tools (Cadence, Sigrity)? > >Thanks and regards, Fabrizio > ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: http://www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu