[SI-LIST] Re: Reducing SSO noise in an FPGA

Bill,
I respectfully disagree with you and agree with Chris.  The SSO problem 
wrt. to a device driver is a chip and package problem.  The round trip 
time from the driver, through the package and out to a BC layer is 
longer than the risetime for almost all packages and devices where this 
is a problem.  SSO is generally a loop inductance issue.  No amount of 
capacitance at the end of a large loop inductance in a power delivery 
system can effect the problem. For the capacitance to be effect, it has 
to be in the package or on the die. As a result, the PCB has no effect 
on instantaneous SSO problems.  You can make the problem worse, but if 
the package and silicon are already hosed, their ain't much you can do 
to make it better.  SSO problems are almost always I/O power issues.  
This is a region of silicon and package design where there are many 
tradeoffs, quite a few of them wrong.  If this portion of the design is 
already broken (and it is in quite a few FPGA, ASICs and even in custom 
devices) then all the BC in the world will not fix it.

BC can deal with lower frequency noise components and lower the overall 
noise floor for a PCB power delivery system.  BC can reduce the power 
impedance profile. BC can even be used to change the resonant frequency 
of a board, if the dielectric constant is higher than FR4.  But BC 
cannot help the classical SSO problem.  If you have real engineering 
data that shows differently, I would enjoy seeing it.

best regards,

scott

-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com



bpanos wrote:

>Chris
>I think it's "guest" not "guess", (might want to check your syntax)
>I disagree with your notion that BC is useless in an SSO applications, Even 
>with
>as you say with good reference pane placement. SSO problems may be manifested 
>by
>supply bounce or ground. Concerning supply bounce in the presence of bypass 
>caps
>and issues with ESL (low ESL caps are not always provided or an option), BC
>could be entertained. To what degree BC would be of a benefit is up to debate.
>Bill
>
>
>
>
>Chris Cheng wrote:
>
>  
>
>>BC is useless to solve packaging SSO or any SSO problem for that matter if
>>you manage your signal reference plane correctly on the PCB. If you choose
>>to use the wrong reference plane for your I/O and then decided to throw
>>money to fix it with BC, be my guess.
>>
>>Chris
>>
>>-----Original Message-----
>>From: bpanos [mailto:bill.panos@xxxxxxxxxxxxxxx]
>>Sent: Friday, June 27, 2003 4:05 PM
>>To: perry.qu@xxxxxxxxxxx
>>Cc: zhang_kun@xxxxxxxxxx; fzanella@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
>>
>>I personally have not tried implementing this particular application, in
>>this fashion, but I wonder how well using BC (buried capacitance) material
>>would work with SSO issues with an FPGA.
>>Granted, there may not be enough capacitance / sq, though with 0.5mil BC it
>>might be an option..
>>Regards,
>>Bill
>>
>>Perry Qu wrote:
>>
>>    
>>
>>>Hi, Zhangkun:
>>>
>>>We have been using 100nF cap extensively in our high speed design (>
>>>      
>>>
>>100MHz) and so far so good. In my understanding, small ESL is the key to
>>make a flat impedance curve in frequency
>>    
>>
>>>range, as explained here many times by Larry Smith and Istvan Novak. Small
>>>      
>>>
>>caps such as NPO 1nF will normally give us  high Q since resonance factor
>>increase when ESL increase, and when
>>    
>>
>>>ESR and C decrease. For NPO cap, it has very small ESR and small C, so if
>>>      
>>>
>>we do not control ESL to very small value, we will end up with high Q. Such
>>high Q cap may cause strong
>>    
>>
>>>anti-resonance when mixed with other cap and/or plane pairs. In our
>>>      
>>>
>>designs, since we can't control ESL very well with special stackup/routing,
>>we use 1nF very carefully.
>>    
>>
>>>Regards
>>>
>>>Perry
>>>
>>>Zhangkun wrote:
>>>
>>>      
>>>
>>>>Dear Zanella
>>>>
>>>>I think 0.1uF and 0.22uF is too large for decoupling. When the frequency
>>>>        
>>>>
>>goes up to 100MHz, these two kind of caps will be of no use. Istvan has
>>writen one paper about measuring caps.
>>    
>>
>>>>Best Regards
>>>>
>>>>Zhangkun
>>>>2003.06.26
>>>>----- Original Message -----
>>>>From: "Fabrizio Zanella" <fzanella@xxxxxxxxxxxx>
>>>>To: <si-list@xxxxxxxxxxxxx>
>>>>Sent: Thursday, June 26, 2003 12:01 AM
>>>>Subject: [SI-LIST] Reducing SSO noise in an FPGA
>>>>
>>>>        
>>>>
>>>>>I would like to hear about experiences regarding methods of reducing
>>>>>simultaneous switching noise in a large FPGA, BGA package.  Let's
>>>>>          
>>>>>
>>assume
>>    
>>
>>>>>a 128bit bus, with a signal frequency of 100MHz.
>>>>>How effective is adding ground planes 2 mils from the VCC planes in
>>>>>reducing SSN? If one uses BC, does every VCC pin in the FPGA require
>>>>>decoupling? And should the caps be tied to the BGA pins with blind
>>>>>          
>>>>>
>>vias
>>    
>>
>>>>>so they can be placed directly under the BGA?  What are the optimal
>>>>>values for the decoupling capacitors, 0.1uf, 0.22uF?
>>>>>
>>>>>Thanks very much and regards,
>>>>>
>>>>>
>>>>>Fabrizio Zanella
>>>>>Principal Hardware Design Engineer
>>>>>Broadbus Technologies
>>>>>fzanella@xxxxxxxxxxxx
>>>>>=20
>>>>>--------------------------------------------------------
>>>>>
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>>>--
>>>Perry Qu
>>>
>>>Design & Qualification       |      600 March Road
>>>Alcatel Canada               |      Ottawa, ON K2K 2E6, Canada
>>>
>>>DID: (613) 7846720           |      FAX: (613) 5993642
>>>
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