Posts for si-list, 07-2003

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» [SI-LIST] how to start high speed PCB design ? -
» [SI-LIST] Re: threshold and 60 Hz -
» [SI-LIST] Re: threshold -
» [SI-LIST] Re: Quasi Static Assumptions -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] IBIS packaging models -
» [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Quasi Static Assumptions -
» [SI-LIST] Re: Quasi Static Assumptions -
» [SI-LIST] Re: PCI-Express Clarifications. -
» [SI-LIST] Re: TDR Transform -
» [SI-LIST] Quasi Static Assumptions -
» [SI-LIST] Re: TDR Transform -
» [SI-LIST] Re: CPWG -
» [SI-LIST] Re: More High Speed Design Books -
» [SI-LIST] More High Speed Design Books -
» [SI-LIST] Re: High Speed Design Books.. -
» [SI-LIST] Re: High Speed Design Books.. -
» [SI-LIST] Re: High Speed Design Books.. -
» [SI-LIST] Re: High Speed Design Books.. -
» [SI-LIST] High Speed Design Books.. -
» [SI-LIST] Re: Capacitors and Anti-resonance -
» [SI-LIST] Re: threshold -
» [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] Out of Office AutoReply: -
» [SI-LIST] Re: Capacitors and Anti-resonance -
» [SI-LIST] Autoreply: -
» [SI-LIST] Re: Capacitors and Anti-resonance -
» [SI-LIST] Re: threshold -
» [SI-LIST] si-list experiment -
» [SI-LIST] Re: threshold -
» [SI-LIST] Re: threshold -
» [SI-LIST] Re: Losses - 2.5Gbps on FR4 -
» [SI-LIST] Re: threshold -
» [SI-LIST] TDR Transform -
» [SI-LIST] Re: threshold -
» [SI-LIST] Re: threshold -
» [SI-LIST] Re: threshold -
» [SI-LIST] QDRII FPGA design -
» [SI-LIST] threshold -
» [SI-LIST] Antw: Re: Capacitors and Anti-resonance -
» [SI-LIST] SI Job Opening -= Foxconn -
» [SI-LIST] Re: OOP problem, changing Reply-To header -
» [SI-LIST] Re: Losses - 2.5Gbps on FR4 -
» [SI-LIST] Re: What is OO'P'? -
» [SI-LIST] OOPS Test -
» [SI-LIST] Re: Capacitors and Anti-resonance -
» [SI-LIST] Re: OOP problem, changing Reply-To header -
» [SI-LIST] Re: What is OO'P'? -
» [SI-LIST] Re: OOP problem, changing Reply-To header -
» [SI-LIST] Bart Bouma/RMD/PHYCOMP/YAGEO is out of the office. -
» [SI-LIST] Re: Anti Vacation Message Grand Experiment -
» [SI-LIST] Re: Anti Vacation Message Grand Experiment -
» [SI-LIST] Anti Vacation Message Grand Experiment -
» [SI-LIST] This is a test OOP -
» [SI-LIST] Re: OOP problem, changing Reply-To header -
» [SI-LIST] Re: A general question of -48V power supply -
» [SI-LIST] Re: OOP problem, changing Reply-To header -
» [SI-LIST] Re: Losses - 2.5Gbps on FR4 -
» [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] Re: OOP problem, changing Reply-To header -
» [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] Re: Losses - 2.5Gbps on FR4 -
» [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] Re: Losses - 2.5Gbps on FR4 -
» [SI-LIST] Re: Losses - 2.5Gbps on FR4 -
» [SI-LIST] Losses - 2.5Gbps on FR4 -
» [SI-LIST] Re: Capacitors and Anti-resonance -
» [SI-LIST] Capacitors and Anti-resonance -
» [SI-LIST] Tantalum chip capacitors in CPCI Platform! -
» [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] ebd to hspice conversion -
» [SI-LIST] New SI jobs at Sigrity -
» [SI-LIST] Presentation on new pcb reference designs and models -
» [SI-LIST] HSPICE Control options for crystal simulations -
» [SI-LIST] Re: least inductance path(return current) -
» [SI-LIST] Re: least inductance path(return current) -
» [SI-LIST] least inductance path(return current) -
» [SI-LIST] pwr/ground -
» [SI-LIST] Re: Crystal Oscillator -
» [SI-LIST] Re: Crystal Oscillator -
» [SI-LIST] CPWG -
» [SI-LIST] Re: Crystal Oscillator -
» [SI-LIST] Re: Conversion from dB to ohm -
» [SI-LIST] Re: Conversion from dB to ohm -
» [SI-LIST] Re: Conversion from dB to ohm -
» [SI-LIST] Conversion from dB to ohm -
» [SI-LIST] Re: OOP problem, changing Reply-To header -
» [SI-LIST] OOP problem, changing Reply-To header -
» [SI-LIST] Re: A general question of -48V power supply -
» [SI-LIST] Re: HS Ground and Power ground seperation -
» [SI-LIST] Re: Spice Tools -
» [SI-LIST] Re: Crystal modelling parameters and parallel resonance frequency formula -
» [SI-LIST] PSPICE to HSPICE -
» [SI-LIST] Re: A general question of -48V power supply -
» [SI-LIST] Spice Tools -
» [SI-LIST] Re: SPICE Tools -
» [SI-LIST] Crystal modelling parameters and parallel resonance frequency formula -
» [SI-LIST] SPICE Tools -
» [SI-LIST] Re: Cadstar SI & Zuken Hot Stage -
» [SI-LIST] Cadstar SI & Zuken Hot Stage -
» [SI-LIST] Re: Power planes -
» [SI-LIST] Re: A general question of -48V power supply -
» [SI-LIST] Re: HS Ground and Power ground seperation -
» [SI-LIST] A general question of -48V power supply -
» [SI-LIST] Re: Mentor Hyperlinx ? -
» [SI-LIST] HS Ground and Power ground seperation -
» [SI-LIST] Re: Fwd: Re: si-list Digest V3 #194 -
» [SI-LIST] Re: AGTL -
» [SI-LIST] Re: Power planes -
» [SI-LIST] Re: Power planes -
» [SI-LIST] AGTL -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: Power planes -
» [SI-LIST] Re: Power planes -
» [SI-LIST] Re: Power planes -
» [SI-LIST] Re: Power planes -
» [SI-LIST] Re: Power planes -
» [SI-LIST] Re: Power planes -
» [SI-LIST] How to calculate output impedance? -
» [SI-LIST] Re: Fwd: Re: si-list Digest V3 #194 -
» [SI-LIST] pl. comment on my stack up -
» [SI-LIST] Re: MECL -
» [SI-LIST] Power planes -
» [SI-LIST] Re: Mentor HyperLynx ? -
» [SI-LIST] Re: how to measure the coupling effect of the coupled lines with vector network analyzer -
» [SI-LIST] Antw: MECL -
» [SI-LIST] Re: MOS cap on chip for DECOUPLING -
» [SI-LIST] 答复: Re: how to measure the coupling effect of the coupled lines with vector network analyzer -
» [SI-LIST] Fwd: Re: si-list Digest V3 #194 -
» [SI-LIST] MECL -
» [SI-LIST] Re: how to measure the coupling effect of the coupled lines with vector network analyzer -
» [SI-LIST] Re: MOS cap on chip for DECOUPLING -
» [SI-LIST] Re: Mentor Hyperlinx ? -
» [SI-LIST] Re: how to measure the coupling effect of the coupled lineswith vector network analyzer -
» [SI-LIST] how to measure the coupling effect of the coupled lines with vector network analyzer -
» [SI-LIST] Re: MOS cap on chip for DECOUPLING -
» [SI-LIST] Re: gnd plane kept close to track -
» [SI-LIST] Re: Mentor Hyperlinx ? -
» [SI-LIST] Re: Mentor Hyperlinx ? -
» [SI-LIST] Re: Please turn off your account when OOP -
» [SI-LIST] Re: 500 MHZ Squarewave (was (no subject)) -
» [SI-LIST] Re: Mentor Hyperlinx ? -
» [SI-LIST] Re: Mentor Hyperlinx ? -
» [SI-LIST] Mentor Hyperlinx ? -
» [SI-LIST] Re: Reduce the slew rate of a driver -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Reduce the slew rate of a driver -
» [SI-LIST] Re: Please turn off your account when OOP -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Please turn off your account when OOP -
» [SI-LIST] Re: si-list Digest V3 #194 -
» (no subject) -
» [SI-LIST] Re: Please turn off your account when OOP -
» [SI-LIST] Re: gnd plane kept close to track -
» [SI-LIST] Re: Please turn off your account when OOP -
» [SI-LIST] Re: gnd plane kept close to track -
» [SI-LIST] Re: Please turn off your account when OOP -
» [SI-LIST] Re: Please turn off your account when OOP -
» [SI-LIST] Please turn off your account when OOP -
» [SI-LIST] Re: gnd plane kept close to track -
» [SI-LIST] Re: MOS cap on chip for DECOUPLING -
» [SI-LIST] Re: MOS cap on chip for DECOUPLING -
» [SI-LIST] Re: MOS cap on chip for DECOUPLING -
» [SI-LIST] Re: Resource for Equivlent Circuit Models -
» [SI-LIST] Calculate Driver Impedance from IBIS -
» [SI-LIST] Hi -
» [SI-LIST] PCI-Express Clarifications. -
» [SI-LIST] Re: gnd plane kept close to track -
» [SI-LIST] Re: gnd plane kept close to track -
» [SI-LIST] Re: MOS cap on chip for DECOUPLING -
» [SI-LIST] Re: gnd plane kept close to track -
» [SI-LIST] trace delay/inch -
» [SI-LIST] MOS cap on chip for DECOUPLING -
» [SI-LIST] Re: Capacitor ESR -
» [SI-LIST] gnd plane kept close to track -
» [SI-LIST] Re: 2.5 D numerical softwares -
» [SI-LIST] Re: PCB signal speed over temperature (and finding Er) -
» [SI-LIST] Cadence Schematic File -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Why we need to add input buffer for RF amplifier? -
» [SI-LIST] SPICE to IBIS Methodology webinar -
» [SI-LIST] Re: Distant Reference Planes Through Other Planes -
» [SI-LIST] Re: Behavioral modeling -
» [SI-LIST] Re: Behavioral modeling -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: Distant Reference Planes Through Other Planes -
» [SI-LIST] Re: Resource for Equivlent Circuit Models -
» [SI-LIST] Re: Resource for Equivlent Circuit Models -
» [SI-LIST] Re: Behavioral modeling -
» [SI-LIST] Re: Capacitor ESR -
» [SI-LIST] Capacitor ESR -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Resource for Equivlent Circuit Models -
» [SI-LIST] Re: PCB signal speed over temperature (and findingEr) -
» [SI-LIST] Re: 2.5 D numerical softwares -
» [SI-LIST] AW: Re: PCB signal speed over temperature -
» [SI-LIST] Re: Tpd Spreadsheet uploaded to si-list web file archives -
» [SI-LIST] Re: 2.5 D numerical softwares -
» [SI-LIST] Re: PCB signal speed over temperature -
» [SI-LIST] Re: PCB signal speed over temperature -
» [SI-LIST] Re: si-list Digest V3 #200 -
» [SI-LIST] Re: Behavioral modeling -
» [SI-LIST] Re: PCB signal speed over temperature -
» [SI-LIST] More jobs at Sigrity! -
» [SI-LIST] Re: Behavioral modeling -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] 2.5 D numerical softwares -
» [SI-LIST] Re: Behavioral modeling -
» [SI-LIST] Re: Behavioral modeling -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Behavioral modeling -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: 2.5Gbps -
» [SI-LIST] Tpd Spreadsheet uploaded to si-list web file archives -
» [SI-LIST] Re: 2.5Gbps -
» [SI-LIST] Re: 2.5Gbps -
» [SI-LIST] Re: Recommendation for high-speed digital input pro tection? -
» [SI-LIST] FPGA interface with PS/2 Mouse -
» [SI-LIST] Re: Recommendation for high-speed digital input protection? -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: Finding Er (Permitivity) -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: Inductance vs. Impedance -
» [SI-LIST] Re: Inductance vs. Impedance -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: Inductance vs. Impedance -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: Finding Er (Permitivity) -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: Finding Er (Permitivity) -
» [SI-LIST] Re: Finding Er (Permitivity) -
» [SI-LIST] Re: LICA caps? -
» [SI-LIST] Re: LICA caps? -
» [SI-LIST] LICA caps? -
» [SI-LIST] Re: Help! -
» [SI-LIST] Re: Recommendation for high-speed digital input protection? -
» [SI-LIST] Re: Finding Er (Permitivity) -
» [SI-LIST] Re: Recommendation for high-speed digital inputprotection? -
» [SI-LIST] Re: Finding Er (Permitivity) -
» [SI-LIST] Re: 2.5Gbps -
» [SI-LIST] Re: Finding Er (Permitivity) -
» [SI-LIST] Re: Finding Er (Permitivity) -
» [SI-LIST] 2.5Gbps -
» [SI-LIST] Re: Finding Er (Permitivity) -
» [SI-LIST] Finding Er (Permitivity) -
» [SI-LIST] spice to ibis -
» [SI-LIST] Help! -
» [SI-LIST] Re: Distant Reference Planes Through Other Planes -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: Distant Reference Planes Through Other Planes -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Distant Reference Planes Through Other Planes -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Any good document for DC offset compensation? -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Battery model -
» [SI-LIST] Re: si-list Digest V3 #194 -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: PCI-Express System Level Trace Impedance Value -
» [SI-LIST] Re: PCI-Express System Level Trace Impedance Value -
» [SI-LIST] Re: HyperlynxSI issue -
» [SI-LIST] Re: PCI-Express System Level Trace Impedance Value -
» [SI-LIST] Microstrip Inductance -
» [SI-LIST] Re: PCI-Express System Level Trace Impedance Value -
» [SI-LIST] Re: ibis in hspice -
» [SI-LIST] R: PCI-Express System Level Trace Impedance Value -
» [SI-LIST] Re: PCI-Express System Level Trace Impedance Value -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] PCI-Express System Level Trace Impedance Value -
» [SI-LIST] Re: op-amp compensation capacitor in digital cmos process -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] R: ibis in hspice -
» [SI-LIST] Re: HyperlynxSI issue -
» [SI-LIST] ibis in hspice -
» [SI-LIST] HyperlynxSI issue -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: op-amp compensation capacitor in digital cmos process -
» [SI-LIST] Job Opening -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: op-amp compensation capacitor in digital cmos process -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] topology for memory bus -
» [SI-LIST] op-amp compensation capacitor in digital cmos process -
» [SI-LIST] AIC7899 pci SCSI controller -
» [SI-LIST] RMCEMC July meeting announcement -
» [SI-LIST] IEEE CPMT Society Phoenix Chapter - Aug 2003 meeting announcement -
» [SI-LIST] Re: Question on DDR SDAM timing spec -
» [SI-LIST] Re: Question on DDR SDAM timing spec -
» [SI-LIST] Re: Question on DDR SDAM timing spec -
» [SI-LIST] Re: Lumped Vs Distributed Model -
» [SI-LIST] Re: extraction tool -
» [SI-LIST] extraction tool -
» [SI-LIST] Re: Differential traces in ebd file -
» [SI-LIST] Re: Question on DDR SDAM timing spec -
» [SI-LIST] DESIGNCON 2004 CALL FOR PAPERS -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Differential traces in ebd file -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: How many Ground pins are enough -
» [SI-LIST] Need Signal Integrity engineer ASAP -
» [SI-LIST] Differential traces in ebd file -
» [SI-LIST] Drivers-Receivers in DSM technologies -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] [Fwd: Re: Re: Reducing SSO noise in an FPGA] -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Reducing SSO noise in an FPGA -
» [SI-LIST] Re: Question on DDR SDAM timing spec -
» [SI-LIST] FW: Field Solver Questions -
» [SI-LIST] Re: Question on DDR SDAM timing spec -
» [SI-LIST] How many Ground pins are enough -
» [SI-LIST] Problems auto unsubbing from list -
» [SI-LIST] Re: Question on DDR SDAM timing spec -
» [SI-LIST] Via anti-pad on 2G signaling -
» [SI-LIST] what is the max trace length for the signals adjecent to the power planes. -
» [SI-LIST] AW: Question on DDR SDAM timing spec -
» [SI-LIST] can a open drain pin drive high impedance? -
» [SI-LIST] please help me defining a problem -
» [SI-LIST] Lumped Vs Distributed Model -
» [SI-LIST] Question on DDR SDAM timing spec -
» [SI-LIST] Re: Measuring Crosstalk -
» [SI-LIST] paper on 9ps high-resolution TDR -
» [SI-LIST] Re: Measuring Crosstalk -
» [SI-LIST] Re: 8 Layer stack up -
» [SI-LIST] Measuring Crosstalk -
» [SI-LIST] Crystal Oscillator -
» [SI-LIST] Re: 8 Layer stack up -
» [SI-LIST] Free webinar on translating SPICE models to IBIS -
» [SI-LIST] Re: Fwd: vgs stress in digital cmos process -
» [SI-LIST] Re: LVDS Routing -
» [SI-LIST] Re: Fwd: vgs stress in digital cmos process -
» [SI-LIST] Re: Fwd: vgs stress in digital cmos process -
» [SI-LIST] Re: Fwd: vgs stress in digital cmos process -
» [SI-LIST] Re: Recommendation for high-speed digital input protection? -
» [SI-LIST] Recommendation for high-speed digital input protection? -
» [SI-LIST] Re: si-list Digest V3 #186 -
» [SI-LIST] LVDS Routing -
» [SI-LIST] Field Solver Questions -
» [SI-LIST] IBIS models for RC Network -
» [SI-LIST] Re: Regulatory testing -
» [SI-LIST] Re: Regulatory testing -
» [SI-LIST] Fwd: vgs stress in digital cmos process -
» [SI-LIST] How many Ground pins are enough -
» [SI-LIST] Re: Regulatory testing -
» [SI-LIST] Regulatory testing -
» [SI-LIST] Re: 8 Layer stack up -
» [SI-LIST] Field Solver Questions -
» [SI-LIST] How many Ground pins are enough -
» [SI-LIST] [Freelists News] crippling outage, partial recovery -
» [SI-LIST] Re: Differential bus emission -
» [SI-LIST] Re: si-list is back in business -
» [SI-LIST] Differential bus emission -
» [SI-LIST] si-list is back in business -
» [SI-LIST] Re: 8 Layer stack up -
» [SI-LIST] Re: need advice on books -
» [SI-LIST] Re: 8 Layer stack up -
» [SI-LIST] Marshall Sherfield Fellowship -
» [SI-LIST] Re: 8 Layer stack up -
» [SI-LIST] Re: rapid io tracking/termination impedance -
» [SI-LIST] Re: how to model an oscillator ? -
» [SI-LIST] Inclusion of RLGC package info in IBIS -
» [SI-LIST] 8 Layer stack up -
» [SI-LIST] Re: how to model an oscillator ? -
» [SI-LIST] measuring internal signals on a chip -
» [SI-LIST] Re: via teardropping effect on signal integrity? -
» [SI-LIST] Re: resistor array compact PCI signals -
» [SI-LIST] Re: via teardropping effect on signal integrity? -
» [SI-LIST] Re: SPI-4 interface -
» [SI-LIST] Re: SPI-4 interface -
» [SI-LIST] SPI-4 interface -
» [SI-LIST] rapid io tracking/termination impedance -
» [SI-LIST] resistor array compact PCI signals -
» [SI-LIST] Re: via teardropping effect on signal integrity? -
» [SI-LIST] Re: via teardropping effect on signal integrity? -
» [SI-LIST] Re: via teardropping effect on signal integrity? -
» [SI-LIST] Re: via teardropping effect on signal integrity? -
» [SI-LIST] Re: via teardropping effect on signal integrity? -
» [SI-LIST] via teardropping effect on signal integrity? -
» [SI-LIST] IBIS Interconnect Modeling Specification - Request for Feedback -
» [SI-LIST] How to control CMOS circuit¡¯s stage-stage DC bias voltage variation with process variation? -
» [SI-LIST] Re: how to model an oscillator ? -
» [SI-LIST] Re: need advice on books -
» [SI-LIST] need advice on books -